tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 18

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
Advance Data Sheet, Rev. 2
SONET/SDH x84/x63 Ultramapper
July 2001
2 The SONET/SDH Ultramapper
(continued)
Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent
MUXs/deMUXs. 84 DS1 inputs in groups of four or 63 E1 input signals in groups of three can feed into individual
M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or direct DS2 inputs, or loopback
deMUXed DS2s.
The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system or it
can be operated in a polled mode.
Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, and G.775.
2.12.1 Receive Direction
The receive DS3 is monitored for loss of clock and checked for loss of signal (LOS) according to T1.231. The B3ZS
decoder accepts either unipolar clock and data or unipolar clock, positive and negative data. It also checks for bipo-
lar coding violations. The transmit DS3 can be looped back into the receive side after B3ZS decoding. The M23
demultiplexer checks for valid DS3 framing by finding the frame alignment pattern (F bits), and then locating the
multiframe alignment signal (M bits). During each M frame, the data stream is checked for the presence of the AIS
(1010) or idle (1100) pattern.
C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link and are available directly at device output via an inter-
nal HDLC receiver. The receiver is composed of a 128-byte FIFO, a CRC-16 frame check sequence (FCS) error
detector, and control circuits.
Within the M23 demultiplexer, there are four performance monitoring counters for F- or M-bit, P-bit, E-bit parity, and
FEBE errors. Each M12 demultiplexer contains two performance monitoring counters.
2.12.2 Transmit Direction
The incoming DS1/E1 clocks are first checked for activity or loss of clock (LOC). The data signals are retimed and
checked for AIS and activity. DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs
from the deMUX path to be looped back. This loopback can be performed automatically or the user can force a
DS1 or E1 loopback.
The four DS1 or three E1 signals for each M12 MUX are fed into single-bit, 16-word-deep FIFOs to synchronize the
signals to the DS2 frame generation clock. The fill level of each FIFO determines the need for bit stuffing its
DS1/E1 input. The M13 can handle DS1/E1 signals with nominal frequency offsets of ± 130 ppm and up to five unit
intervals peak jitter. The DS2/DS3 transmit clock is used to derive the clock source for DS2 frame generation.
The M23 multiplexer generates a transmit DS3 frame, and fills the information bits in the frame with data from the
seven DS2 select blocks. The M23 MUX can be provisioned to operate in either the M23 mode or the C-bit parity
mode. It contains seven DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need for bit
stuffing its DS2 input.
The transmit DS3 output can either be in the form of unipolar clock and data or unipolar clock, positive and negative
data. The DS3 data is B3ZS encoded and can be looped back from the receive DS3 input.
2.13 E13/E23 Multiplexer
The information on the E13/E23 multiplexer is not available at this time.
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Agere Systems Inc.