tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 35

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

Advance Data Sheet, Rev. 2
July 2001
3 Pin Information
Table 1. Pin Descriptions (continued)
* O
† Transmit path convention is toward the high-speed fiber output. Note that CHIRX signals are labeled “Receive,” as seen from the cross con-
Agere Systems Inc.
W34, W33,
I/O
I
I
nect perspective.
M29, K33,
M33, P29,
M34, P30,
N34, R29,
R34, U29,
U30, U32,
J34, M30,
M32, L34,
N33, P32,
P33, R30,
P34, R32,
T29, R33,
U33, V33,
V32, V30,
H34, L30,
L32, K34,
L33, N29,
T33, T34,
V29, Y34
D
U
J32, J33,
1
; I/O
indicates internal pull-up.
2
indicates external pull-up recommended (unused or system required),
W29
Y32
Y33
Pin
indicates external pull-down recommended (unused or system required),
D
indicate internal pull-down,
CHIRXDATA[42:1]
CHIRXGTCLK
CHIRXGCLK
CHIRXGFS
Symbol
(continued)
CHI Transmit PATH Direction (45 total, last 3 not indexed)
Multifunction System Interface (continued)
Type I/O*
—
—
—
—
I
I
I
I
Configurable Inputs to the Internal Cross Connect.
Switching modes:
CHI:
Receive system data or data and signaling input at
2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s.
Parallel system bus:
CHIRXDATA[16:1]: Receive system data bus input is assigned to
the first 16 inputs (19.44 Mbits/s). MSB—CHIRXDATA[16]
through LSB to CHIRXDATA[1].
CHIRXDATA[42:17]: Not used in PSB mode only.
Transport modes:
Framer—LIU: CHIRXDATA[30:1] Received negative-rail
DS1/E1 line data input or 8k frame sync input.
M12 or E12: not used.
VT Mapper: 8 k SYNC for DS1/E1 or 2 k sync signal for VC.
M23 or E23: Stuff request input in demand clocking mode.
CHI: global transmit line clock input. Externally supplied
1.544 MHz for DS1 and 2.048 MHz low jitter clock phase-locked
to the receive CHI system clock (optional).
Parallel system bus: global transmit line clock input. Externally
supplied 1.544 MHz for DS1 and 2.048 MHz low jitter clock
phase-locked to the parallel system bus receive clock (optional).
CHI: receive global system clock input (4.096 MHz, 8.192 MHz,
or 16.384 MHz).
Parallel system bus: Receive global clock input (19.44 MHz).
CHI: Receive system frame sync input.
Parallel system bus: Receive system frame sync input.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Description
†
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