tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 41

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

Advance Data Sheet, Rev. 2
July 2001
3 Pin Information
Table 1. Pin Descriptions (continued)
* O
Agere Systems Inc.
I/O
I
I
D
U
1
; I/O
indicates internal pull-up.
2
indicates external pull-up recommended (unused or system required),
AM21
AM23
AM24
AM15
AM14
AP22
AN22
AK21
AP23
AN23
AP24
AN24
AP25
AK17
AL17
AJ21
AJ22
AJ15
AJ14
AJ16
indicates external pull-down recommended (unused or system required),
Pin
D
indicate internal pull-down,
SCANMODE
TSTPHASE
IC3STATEN
TSTSFTLD
TSTMODE
ETOGGLE
SCAN_EN
EXDNUP
BYPASS
Symbol
PMRST
ECSEL
RSTN
TRST
SCK1
SCK2
I
TMS
TDO
TCK
TDI
DD
(continued)
Q
Type
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
General Purpose Interface (13)
I/O
I/O*
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
U
I
U
U
U
U
D
D
D
D
D
D
D
D
D
D
D
D
CDR Interface (7)
D
Chip Reset (Active-Low).
Performance Monitor Reset.
JTAG Test Clock. This signal provides timing for test opera-
tions.
JTAG Test Data In. JTAG test data input signal, sampled on
the rising edge of TCK.
JTAG Test Mode Select. Controls test operations. TMS is
sampled on the rising edge of TCK.
JTAG Test Reset (Active-Low). This signal provides an
asynchronous reset.
JTAG Test Data Out. JTAG test data output signal is updated
on the falling edge of TCK. The TDO output is 3-stated
except when scanning out test data.
Disable Output Capability of all Bidirectional and 3-State
Output Buffers (Active-Low).
(Test Only.) Scan Clock 1.
(Test Only.) Scan Clock 2.
(Test Only.) Scan Enable (Active-High).
(Test Only.) Serial Scan Input for Testing (Active-High).
(Test Only.) I
(Test Only.) Enables functional bypassing of the clock syn-
thesis with a test clock. Active-high.
(Test Only.) Controls bypass of 32 PLL-generated phases
with 32 low-speed phases, generated by test logic. Active-
high.
(Test Only.) Enables external test control of 155 MHz clock
phase selection through ETOGGLE and EXDNUP inputs.
Active-high.
(Test Only.) Moves 155 MHz clock selection one phase per
positive pulse > 20 ns. Active + pulse.
(Test Only.) Direction of phase change.
0 = down; 1 = up.
(Test Only.) Enables test mode for CDR and PLLs.
(Test Only.) Enables CDR test mode shift register.
TMXF84622 155 Mbits/s/622 Mbits/s Interface
DD
Q Input (Active-High).
SONET/SDH x84/x63 Ultramapper
Description
41