k7r321882m Samsung Semiconductor, Inc., k7r321882m Datasheet
k7r321882m
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k7r321882m Summary of contents
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... K7R323682M K7R321882M K7R320982M Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDR Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Pin name change from DLL to Doff. 2. Vddq range change from 1.5V to 1.5V~1.8V. 3. Update JTAG test conditions. 4. Reserved pin for high density name change from NC to Vss/SA 5. Delete AC test condition about Clock Input timing Reference Level 6 ...
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... WRITE DRIVER 19 (or 20) 1Mx36 (2Mx18) MEMORY ARRAY SELECT OUTPUT CONTROL - SRAM Part Cycle Access Number Time Time K7R323682M-FC20 5.0 0.45 K7R323682M-FC16 6.0 0.50 K7R321882M-FC20 5.0 0.45 K7R321882M-FC16 6.0 0.50 K7R320982M-FC20 5.0 0.45 K7R320982M-FC16 6.0 0. (or 36) (or 36) 36 (or 18) Q(Data Out) CQ (Echo Clock out) Unit Dec. 2003 Rev 2.0 ...
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... K7R323682M K7R321882M K7R320982M PIN CONFIGURATIONS (TOP VIEW /SA* NC/SA Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 F Q30 Q21 D21 G D30 D22 Q22 H Doff V V REF DDQ J D31 Q31 D23 K Q32 D32 Q23 L Q33 ...
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... K7R323682M K7R321882M K7R320982M PIN CONFIGURATIONS (TOP VIEW) K7R321882M(2Mx18 /SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H Doff V V REF DDQ D14 Q14 L NC Q15 D15 D16 ...
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... K7R323682M K7R321882M K7R320982M PIN CONFIGURATIONS (TOP VIEW) K7R320982M(4Mx9 /SA Doff V V REF DDQ ...
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... The K7R323682M,K7R321882M and K7R320982M are 37,748,736-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for K7R323682M, 2,097,152 words by 18 bits for K7R321882M and 4,194,304 words by 9bits for K7R320982M. The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports with the same cycle ...
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... Circuitry automatically resets the DLL when absence of input clock is detected. Single Clock Mode K7R323682M,K7R321882M and K7R320982M can be operated with the single clock pair K and K, insted for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. After power up, this device can’ ...
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... K7R323682M K7R321882M K7R320982M READ NOP READ LOAD NEW READ READ ADDRESS ALWAYS (FIXED) DDR READ Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "READ" refers to read active status with R=Low, "READ " refers to read inactive status with R=high. "WRITE" and " WRITE" are the same case. ...
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... K7R323682M K7R321882M K7R320982M TRUTH TABLES SYNCHRONOUS TRUTH TABLE Stopped X X Previous state Din at K(t) X Notes means "Don t Care". 2. The rising edge of clock is symbolized Before enter into clock stop status, all pending read and write operations will be completed. ...
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... K7R323682M K7R321882M K7R320982M ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification is not implied ...
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... K7R323682M K7R321882M K7R320982M AC ELECTRICAL CHARACTERISTICS PARAMETER Input High Voltage Input Low Voltage Notes: 1. This condition is for AC function test only, not for AC parameter test maintain a valid level, the transitioning edge of the input must : a) Sustain a constant slew rate from the current AC level through the target AC level, V ...
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... K7R323682M K7R321882M K7R320982M AC TIMING CHARACTERISTICS PARAMETER Clock Clock Cycle Time ( Clock Phase Jitter ( Clock High Time ( Clock Low Time ( Clock to Clock ( Clock to data clock ( DLL Lock Time ( Static to DLL reset ...
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... K7R323682M K7R321882M K7R320982M PIN CAPACITANCE PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance Note: 1. Parameters are tested with RQ=250 2. Periodically sampled and not 100% tested. THERMAL RESISTANCE PRMETER Junction to Ambient Junction to Case Junction to Pins Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance ...
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... K7R323682M K7R321882M K7R320982M TIMING WAVE FORMS OF READ AND NOP READ t KHKH t KLKH K t KHKL IVKH KHIX R Q(Data Out) t KHKH C t KHKL Note : 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled one cycle after a NOP. ...
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... K7R323682M K7R321882M K7R320982M TIMING WAVE FORMS OF READ, WRITE AND NOP READ WRITE D(Data In) D2-1 D2-2 Q(Data Out Note address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2. Write data is forwarded immediately as read results. 2.BWx ( NWx ) assumed active. 1Mx36 & 2Mx18 & 4Mx9 QDR ...
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... K7R323682M K7R321882M K7R320982M IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7R323682M K7R321882M K7R320982M SCAN REGISTER DEFINITION Part Instruction Register 1Mx36 3 bits 2Mx18 3 bits 4Mx9 3 bits ID REGISTER DEFINITION Revision Number Part (31:29) 1Mx36 000 2Mx18 000 4Mx9 000 Note : Part Configuration /def=010 for 36Mb, /wx=11 for x36, 10 for x18, 00 for x9. /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O ...
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... K7R323682M K7R321882M K7R320982M JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7R323682M K7R321882M K7R320982M 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 0.1 C 1.3 0.1 D 0.35 0.05 1Mx36 & 2Mx18 & 4Mx9 QDR Note Symbol SRAM B Top View ...