k7r321882m Samsung Semiconductor, Inc., k7r321882m Datasheet - Page 14

• Manufacturer Part Number: k7r321882m
• Description: 1mx36-bit, 2mx18-bit, 4mx9-bit Qdrtm Ii B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

TIMING WAVE FORMS OF WRITE AND NOP
K7R323682M
K7R321882M
K7R320982M
TIMING WAVE FORMS OF READ AND NOP
Note : 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
Note: 1.D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+ 0.
K
K
SA
R
Q(Data Out)
C
C
CQ
CQ
K
K
SA
W
D(Data In)
2. Outputs are disabled one cycle after a NOP.
2. BWx ( NWx ) assumed active.
t
IVKH
t
IVKH
A1
D1-1
READ
t
KHIX
t
KHIX
t
KHKL
t
KHKL
t
KHKL
t
KHKH
t
D1-2
KHKH
A1
t
WRITE
KHKH
t
t
KLKH
KLKH
t
KLKH
A2
D2-1
READ
t
t
K HKH
KH K H
t
t
KH K H
A V K H
t
KHCH
D2-2
A2
1Mx36 & 2Mx18 & 4Mx9 QDR
WRITE
t
CHQX
t
t
C H C Q V
CHQV
1
t
CHCQX
Q1-1
t
C QHQV
- 14 -
NOP
NOP
t
KHIX
t
CHQV
Q1-2
t
CHQX
t
CQHQX
t
A V K H
t
DVKH
D3-1
A3
Q2-1
t
READ
KHAX
t
CHCQV
t
D3-2
C H C Q X
A3
Q2-2
t
WRITE
KHDX
t
KHAX
t
CHQZ
NOP
NOP
TM
Don t Care
Don t Care
II b2 SRAM
Dec. 2003
Undefined
Undefined
Q3-1
Rev 2.0