k7r321882m Samsung Semiconductor, Inc., k7r321882m Datasheet - Page 7

• Manufacturer Part Number: k7r321882m
• Description: 1mx36-bit, 2mx18-bit, 4mx9-bit Qdrtm Ii B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

Clock Consideration
K7R323682M
K7R321882M
K7R320982M
Write Operations
Programmable Impedance Output Buffer Operation
Single Clock Mode
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 9-bit or 8-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7R323682M,K7R321882M and K7R320982M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7R323682M, K7R321882M and K7R320982M support byte write operations.
With activating BW
In K7R321882M, BW
And in K7R323682M BW
And in K7R320982M BW controls write operation to D0:D8.
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav-
ior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Echo clock operation
K7R323682M,K7R321882M and K7R320982M utlizes internal DLL(Delay-Locked Loops) for maximum output
data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
K7R323682M,K7R321882M and K7R320982M can be operated with the single clock pair K and K,
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and C Q,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
during operation.
insted of C or C for output clocks.
0
resistor will give an output impedance of 50 .
or BW
0
controls write operation to D0:D8, BW
2
1
controls write operation to D18:D26, BW
( BW
2
or BW
3 )
in write cycle, only one byte of input data is presented.
1Mx36 & 2Mx18 & 4Mx9 QDR
1
controls write operation to D9:D17.
- 7 -
3
controls write operation to D27:D35.
SS
through a precision resistor(RQ).
TM
II b2 SRAM
Dec. 2003
Rev 2.0