k7r321884c Samsung Semiconductor, Inc., k7r321884c Datasheet - Page 12

• Manufacturer Part Number: k7r321884c
• Description: 1mx36-bit, 2mx18 And 4mx9-bit Qdr Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R323684C
K7R321884C
K7R320984C
AC ELECTRICAL CHARACTERISTICS
Notes: 1. This condition is for AC function test only, not for AC parameter test.
AC TIMING CHARACTERISTICS
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
Clock
Clock Cycle Time (K, K, C, C)
Clock Phase Jitter (K, K, C, C)
Clock High Time (K, K, C, C)
Clock Low Time (K, K, C, C)
Clock to Clock (K↑ → K↑, C↑ → C↑)
Clock to data clock (K↑ → C↑, K↑→ C↑)
DLL Lock Time (K, C)
K Static to DLL reset
Output Times
C, C High to Output Valid
C, C High to Output Hold
C, C High to Echo Clock Valid
C, C High to Echo Clock Hold
CQ, CQ High to Output Valid
CQ, CQ High to Output Hold
C, High to Output High-Z
C, High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
Input High Voltage
Input Low Voltage
2. Control singles are R, W,BW
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
2. To maintain a valid level, the transiting edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, V
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, V
The specs as shown do not imply bus contention because tCHQX
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
The data sheet parameters reflect tester guard bands and test setup variations.
PARAMETER
PARAMETER
0
,BW
SYMBOL
1
t
t
t
t
t
t
t
KC reset
t
t
t
t
t
t
CHCQV
CHCQX
CQHQV
CQHQX
t
t
t
t
t
KC lock
CHQX1
t
t
and (BW
KC var
t
t
KHCH
CHQV
CHQX
CHQZ
KHKH
KHKL
KLKH
KHKH
AVKH
DVKH
KHAX
KHDX
IVKH
KHIX
2
, BW
-0.45
-0.45
-0.25
-0.45
1024
3.00
1.35
0.00
0.40
0.40
0.28
0.40
0.40
0.28
MIN
1.2
1.2
30
3
, also for x36 and BW for x9)
SYMBOL
V
V
1Mx36, 2Mx18 & 4Mx9 QDR
IH
IL
-33
(AC)
(AC)
MAX
8.40
0.20
1.30
0.45
0.45
0.25
0.45
- 12 -
1
is a MIN parameter that is worst case at totally different test conditions
1
is bigger than tCHQZ.
1024
-0.45
-0.45
-0.27
-0.45
3.30
1.32
1.32
1.49
0.00
0.40
0.40
0.30
0.40
0.40
0.30
MIN
30
V
-30
REF
MIN
-
MAX
+ 0.2
8.40
0.20
1.45
0.45
0.45
0.27
0.45
IL(AC)
IL(DC)
or V
or V
IH(AC)
1024
-0.45
-0.45
-0.30
-0.45
4.00
1.60
1.60
1.80
0.00
0.50
0.50
0.35
0.50
0.50
0.35
MIN
IH(DC)
30
V
REF
Rev. 1.1 August 2006
MAX
-25
-
- 0.2
MAX
8.40
0.20
1.80
0.45
0.45
0.30
0.45
TM
UNIT
II b4 SRAM
V
V
UNIT
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1,2
1,2
NOTE
5
6
3
3
7
7
3
3
2