k7r321884c Samsung Semiconductor, Inc., k7r321884c Datasheet - Page 9

• Manufacturer Part Number: k7r321884c
• Description: 1mx36-bit, 2mx18 And 4mx9-bit Qdr Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
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* Notes: When the operating frequency is changed, DLL reset should be required again.
K7R323684C
K7R321884C
K7R320984C
Detail Specification of Power-Up Sequence in QDRII SRAM
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
Power up & Initialization Sequence (Doff pin controlled)
Status
Status
Power-Up Sequence
DLL Constraints
V
V
K,K
V
V
REF
K,K
DDQ
V
V
Doff
DD
DDQ
REF
DD
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var.
After DLL reset again, the minimum 1024 cycles of clock input is needed to lock the DLL.
1. Apply power and keep Doff at low state (All other inputs may be undefined)
2. Just after the stable power and clock (K, K, C, C), take Doff to be high.
3. The additional 1024cycles of clock input is required to lock the DLL after enabling DLL
2. The lower end of the frequency at which the DLL can operate is 8.4ns.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
* Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
and this may cause the failure in the initial stage.
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
Power-Up
Power-Up
Unstable
CLKstage
Unstable
CLKstage
1Mx36, 2Mx18 & 4Mx9 QDR
- 9 -
Stop Clock
Min 30ns
must be stable
Inputs Clock
DLL Locking Range
must be stable
Inputs Clock
1024 cycle
DLL Locking Range
1024 cycle
Rev. 1.1 August 2006
TM
II b4 SRAM
Any
Command
Any
Command