k7r321884c Samsung Semiconductor, Inc., k7r321884c Datasheet - Page 17

• Manufacturer Part Number: k7r321884c
• Description: 1mx36-bit, 2mx18 And 4mx9-bit Qdr Ii B4 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7R323684C
K7R321884C
K7R320984C
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg-
ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to V
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to V
TAP Controller State Diagram
JTAG Block Diagram
TMS
TCK
C,C
A,D
K,K
CQ
CQ
TDI
Q
DD
through a resistor. TDO should be left unconnected.
1
0
BYPASS Reg.
Identification Reg.
Instruction Reg.
Control Signals
Test Logic Reset
TAP Controller
Run Test Idle
SRAM
CORE
0
1
1
1
1
1Mx36, 2Mx18 & 4Mx9 QDR
TDO
Capture DR
Update DR
- 17 -
Select DR
Pause DR
JTAG Instruction Coding
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other
2. Places DQs in Hi-Z in order to sample all input data regardless of other
3. TDI is sampled as an input to the first ID register to allow for the serial shift
4. Bypass register is initiated to V
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
Exit1 DR
Exit2 DR
Shift DR
IR2 IR1 IR0
0
0
0
0
1
1
1
1
0
of the external TDI data.
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
SRAM inputs.
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
SS
to preclude mid level input. TMS and TDI are designed so an
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EXTEST
0
0
IDCODE
SAMPLE-Z
RESERVED
SAMPLE
RESERVED
RESERVED
BYPASS
1
0
Instruction
1
1
SS
when BYPASS instruction is invoked. The
Rev. 1.1 August 2006
Boundary Scan Register
Identification Register
Boundary Scan Register
Do Not Use
Boundary Scan Register
Do Not Use
Do Not Use
Bypass Register
Capture IR
Update IR
Pause IR
Select IR
Exit1 IR
Exit2 IR
Shift IR
0
TDO Output
TM
0
1
0
1
1
1
II b4 SRAM
0
0
0
0
1
Notes
1
3
2
6
5
6
6
4