m35b32 STMicroelectronics, m35b32 Datasheet - Page 27

• Manufacturer Part Number: m35b32
• Description: 32 Kbit, 256-byte Page, Fast Program Eeprom Memory Accessed By Spi Bus Interface
• Manufacturer: STMicroelectronics

M35B32
6.10
Page Erase (PE)
The Page Erase (PE) instruction is mostly dedicated to the Event sector, as this sector must
be erased before executing a Page Program instruction (fast programming time).
The Page Erase instruction resets to 1 (FFh) all bits inside the chosen page. Before it can be
accepted, a Write Enable (WREN) instruction must have been executed previously. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL).
The Page Erase (PE) instruction is entered by driving Chip Select (S) low, followed by the
instruction code, and two address bytes on Serial Data Input (D). Any address inside the
Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven
low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven high after the eighth bit of the last address byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven high, the self-timed Page Erase cycle (whose duration is t
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is at 1 during the
self-timed Page Erase cycle, and it is at 0 when the cycle is complete. The Write Enable
Latch (WEL) bit is also reset (or not) once the self-timed Page Earse cycle is complete,
depending on the logical level applied on the W input pin and the value of the decoded
address, as shown in
A Page Erase (PE) instruction applied to a page in Event sector that is Hardware Protected
is not executed.
Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 15. Page Erase (PE) instruction sequence
3. Address bits A15 to A12 are Don’t Care.
S
C
D
Table
0
1
4).
2
Doc ID 18391 Rev 3
Instruction
3
4
Figure
5
6
7
15.
MSB
15 14
8
9
16-bit address
2
29 30 31
1
0
PE
Instructions
) is initiated.
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