CM6802A CHAMP [Champion Microelectronic Corp.], CM6802A Datasheet - Page 16

• Manufacturer Part Number: CM6802A
• Description: EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER
• Manufacturer: CHAMP [Champion Microelectronic Corp.]

http://www.championmicro.com.tw
Vrms Description:
VRMS pin is designed for the following functions:
1.
2.
3.
Current Error Amplifier, IEAO
cycle to keep the average current through the boost inductor
a linear function of the line voltage. At the inverting input to
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I
negative voltage on I
flowing in the PFC circuit, and is typically derived from a
current sense resistor in series with the negative terminal of
the input bridge rectifier.
In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier
is a virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC, an
increase in positive current from the gain modulator will
cause the output stage to increase its duty cycle until the
voltage on I
increased current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease, to achieve a
less negative voltage on the I
Error Amplifier Compensation
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points.
2009/11/02
The PWM loading of the PFC can be modeled as a
The current error amplifier’s output controls the PFC duty
VRMS is used to detect the AC Brown Out (Also, we
can call it PFC brown out.). When VRMS is less than 1.0
V +/-5%, PFCOUT will be turned off and VEAO will be
softly discharged toward 0 Volt. When VRMS is greater
than 1.25V +/-5%, PFCOUT is enabled and VEAO is
released.
VRMS also is used to determine if the AC Line is high
line or it is low line. If VRMS is above 2.5V +/- 5%, IC
will recognize it is high line the. If VRMS is below 2.25V
+/- 5%, it is low line. Between 2V <=~ Vrms <=~ 2.25V,
it is the hysteresis.
At High Line and Light Load, 380V to 304V (Vfb
threshold moves from 2.5V to 2V) is prohibited of
CM6802A/B ; 380V to 342V (Vfb threshold moves from
2.5V to 2.25V) is prohibited of CM6802AH/BH.
At Low Line and Light Load, 380V to 304V (Vfb
threshold moves from 2.5V to 2V) is enable of
CM6802A/B ; 380V to 342V (Vfb threshold moves from
2.5V to 2.25V) is enable of CM6802AH/BH. It provides
ZVS-Like performance.
the
SENSE
Rev. 1.4
proper
is adequately negative to cancel this
SENSE
Design for High Efficient Power Supply at both Full Load and Light Load
represents the sum of all currents
compensation
SENSE
pin.
CM6802A/B/AH/BH
Champion Microelectronic Corporation
of
SENSE
EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER
the
pin. The
two
a soft-start characteristic on the PFC: as the reference voltage
comes up from zero volts, it creates a differentiated voltage on
I
duty cycle on its boost converter.
PFC Brown Out
voltage and inhibits the PFC and PFC error amplifier output,
Veao is pulled down during the Vrms is lower than threshold. If
this voltage on Vrms is less than its nominal 1.25V. Once this
voltage reaches 1.25V, which corresponds to the PFC input rms
is around 88Vac. It is a hysteresis comparator and its lower
threshold is 1V. After PFC Brown Out conditions are removed,
the system will initiate the start up sequence with the proper soft
start rate set by SS (pin 5).
Cycle-By-Cycle Current Limiter and
Selecting R
loop, is a direct input to the cycle-by-cycle current limiter for the
PFC section. Should the input voltage at this pin ever be more
negative than –1V, the output of the PFC will be disabled until
the protection flip-flop is reset by the clock pulse at the start of
the next PFC power cycle.
the steady state, line input current x R
the maximum output voltage of the gain modulator is I
7.75K≒ 0.8V during the steady state, R
will be limited below 0.8V as well. When VEAO reaches
maximum VEAO which is 6V, Isense can reach 0.8V. At 100%
load, VEAO should be around 4.5V and ISENSE average peak
is 0.6V. It will provide the optimal dynamic response + tolerance
of the components.
Therefore, to choose R
R
maximum input rms power is 200Watt, R
x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer needs to
consider the parasitic resistance and the margin of the power
supply and dynamic response. Assume R
R
PFC OVP
In the CM6802A/B/AH/BH, PFC OVP comparator serves to
protect the power circuit from being subjected to excessive
voltages if the load should suddenly change. A resistor divider
from the high voltage DC output of the PFC is fed to VFB. When
the voltage on VFB exceeds ~ 2.85V, the PFC output driver is
shut down. The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below ~ 2.55V. The VFB
power components and the CM6802A/B/AH/BH are within their
safe operating voltages, but not so low as to interfere with the
boost voltage regulation loop.
EAO
SENSE
SENSE
The current loop compensation is returned to V
For example, if the minimum input voltage is 80VAC, and the
The PFC Brown Out comparator monitors the Vrms (pin 4)
The I
R
S
which prevents the PFC from immediately demanding a full
is the sensing resistor of the PFC boost converter. During
= 139 mOhm.
+ R
SENSE
Parasitic
pin, as well as being a part of the current feedback
(Dynamic Soft PFC/Green PWM)
SENSE
=0.6V x Vinpeak / (2 x Line Input power)
(PFC Brown Out Comparator)
SENSE
, we use the following equation:
SENSE
SENSE
SENSE
Parasitic
= I
x line input current
mul
+ R
REF
x 7.75K. Since
Parasitic
= 30 mOhm,
to produce
mul
16
= (0.6V
max x