MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 13

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

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BGRNT#
IRL3
IRL2
IRL1
IRL0
READY#
MEXC#
BREQ#
Symbol
BUS REQUEST
BUS GRANT
INTERRUPT RE-
QUEST LEVEL
EXTERNAL
READY
MEMORY
EXCEPTION
Pin name
O
I
I
I
I
I/O
Bus request signal.
When the BREQ# signal is asserted by external bus mastering, the
CPU releases the bus as shown below upon termination of the current
bus cycle:
(1)When executing the Atomic Load Store instruction, the CPU releas-
(2)When loading or storing a double word:
(3)When storing data at the 8/16-bit bus width:
(4)When loading data at the 8/16-bit bus width:
Bus grant signal.
Upon reception of a bus request (BREQ#), the BGRNT# signal is as-
serted to notify the external device of the bus released status.
Interrupt input pins.
These pins are used to input an encoded interrupt level. They handle
a group of asynchronous input signals, notifying the IU (integer unit) of
an interrupt level only when the same level is detected twice at the fall
of an external clock pulse. IRL = 0000
interrupt and a nonmaskable interrupt as defined in the SPARC archi-
tecture. IRL must be determined for priority by an external circuit and
must be held until confirmed by the CPU.
Ready signal input pin.
Input the “L” level signal to upon completion of a bus cycle.
Upon reception of READY#=“L”, the CPU starts the next bus cycle.
Note, however, that the“L” input to this pin is not necessary when the
internal wait state generator circuit is used.
For burst transfer, instruction fetch or data load using an 8-bit bus, in-
struction fetch or data load using an 16-bit bus, the pin must input the
ready signal for the prescribed number of times whenever the address
strobe signal is asserted.
Memory access exception pin.
If this pin inputs the “L” level signal in the same cycle as the ready sig-
nal input, the CPU handles it as an instruction access or data access
exception to generate a trap. The operation of the device is unpredict-
able if the MEXC# signal is asserted at a timing other than the same
cycle as the ready signal input. (An exception occurring with the PSR
ET bit set to “0” results in an error state.)
If the BREQ# signal is asserted at the first word, the CPU releases
the bus after transfer of the first word. If the BREQ# signal is assert-
ed in the bus cycle for the second word, the CPU releases the bus
after transfer of the second word.
The CPU releases the bus after transfer of that size of data which is
handled by the instruction (for example, after writing 8-bit data four
times when storing word data using an 8-bit bus).
The CPU releases the bus after transfer of one word.
When the ASISEL pin is at the “L” level, the “L” input to the AS# pin
is prohibited in the bus grant state.
es the bus after completing both of loading and storing.
Function
MB86830 Series
2
and IRL = 1111
(2)
indicate no
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