MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 61

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

controller also controls the RAS and CAS to place DRAM in the self-refresh mode when the processor enters the
sleep mode (low power consumption mode).
The MB86836 has no DRAM controller.
10. Interrupt Controller (IRC)
The interrupt controller (IRC) accepts interrupts inputs through eight channels, depending on the trigger mode and
mask bit set for each of the channels. When accepting an interrupt, the interrupt controller encodes it according
to the interrupt priority level and outputs the interrupt level to the processor. The interrupt level remains held unless
it is cleared by the processor. The processor is not therefore informed of the next interrupt.
11. Multiplier Circuit
The CLKSEL0, CLKSEL1, and CLKSEL2 pins can be used to select the multiplier circuit to be used. The 1, 2,
12. IU (Integer Unit) Dedicated Registers (Not Memory Mapped)
(1)Processor Status Register (PSR)
bit 23 to bit 20 :Integer condition code [icc] (n:Negative
bit 19 to bit 12 :Reserved[“0”Write, Don’t care for read]
bit 11 to bit 8
bit 7
bit 6
bit 5
bit 4 to bit 3
bit 2 to bit 0
X:Don’t care
(2)Window Invalid Mask Register (WIM)
bit 31 to bit 8
bit 7 to bit 0
X:Don’t care
(3)Trap Base Register (TBR)
bit 31 to bit 12 :Trap base address [TBA] (RST
bit 11 to bit 4
X:Don’t care
3, 4, or 5 multiplier circuits are supported, which allow the processor to run faster.
bit
bit
bit
31
31
31
0 0 0 0
:Processor Interrupt Level [PIL] (Value
:Supervisor Mode [S] (Supervisor
:Prior S Mode [PS]
:Enable Trap [ET] (Enable
:Reserved [“0”Write, Don’t care for read]
:Current Window Point [CWP] (Value
:Reserved [“0”Write, Don’t care for read]
:Window mask [w7 to w0] (Invalid
:Trap type [tt] (RST
28 27
H
1 1 1 1
H
24 23
n
z
X)
icc
TBA
Reserved
v
1, Disable
20 19
c
X)
1, User
1, Valid
Reserved
0 to 7, RST
1 to 15, RST
0, RST
1, z:Zero
0, RST
0, RST
12 11
0)
X)
1, v:Overflow
12
1)
X)
X)
PIL
11
MB86830 Series
8
8
S
7
w7 w6 w5 w4 w3 w2 w1 w0
7
PS ET Reserved
1, c:Carry
6
6
tt
5
5
4
4
1)
4
3
3 2
2
3
0 0 0 0
CWP
1
0
0
0
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