MB86831 FUJITSU [Fujitsu Component Limited.], MB86831 Datasheet - Page 60

• Manufacturer Part Number: MB86831
• Description: 32-bit Embedded Controller
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

60
MB86830 Series
8. Bus Interface
The bus interface unit (BIU) is designed to simplify the interface between the MB86830 series and other parts of
the system. The non-multiplexed address bus and data bus allow a high-speed system to be constructed easily.
Also, the internal circuitry allows such a system to be constructed with a minimum of external hardware.
The bus interface supports programmable wait state generation, chip select output by address decoding, same-
page detection for supporting page mode DRAM, booting from 8/16/32-bit memory, and a automatic reload timer
for refreshing DRAM. In addition, the burst mode can be used to perform cache line fill operation at high speed.
9. DRAM Controller
With the DRAM controller controlling DRAM, the MB86830 series can write/read data to/from DRAM. The DRAM
controller can control up to four banks on the MB86831/832/834 or only one bank on the MB86833/835. The fast
page mode, DRAM mode, or EDO DRAM mode can be selected depending on the register setting. The DRAM
• The composition of the data cache (For MB86832).
• The composition of the instruction cash (For MB86832).
31
31
Lock, valid, LRU
Lock, valid, LRU
Address tag
Address tag
Address tag
Address tag
.
.
.
.
12
12
(Tag)
(Tag)
0
0
127
127
0
0
Sub-block
Sub-block
8 entry
8 entry
.
.
.
.
SET 1
SET 1
SET 2
SET 2
(Entry)
(Entry)