16C6N4 RENESAS [Renesas Technology Corp], 16C6N4 Datasheet - Page 78

• Manufacturer Part Number: 16C6N4
• Description: Renesas MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
NOTES:
Switching Characteristics
(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.67 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-HLDA)
Symbol
3. This standard value shows the timing when the
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – V
by a circuit of the right figure.
For example, when V
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 V
Aug 25, 2006
0.5 ✕ 10
f(BCLK)
(n – 0.5) ✕ 10
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
f(BCLK)
9
– 10 [ns]
page 78 of 88
9
– 40 [ns]
OL
OL
/ V
= 0.2 V
CC
Parameter
)
CC
/ V
CC
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
CC
, C = 30 pF,
) = 6.7 ns.
(3)
(3)
Figure 5.21
Measuring
Condition
5. Electric Characteristics (Normal-ver.)
DBi
(NOTE 1)
(NOTE 2)
(NOTE 1)
Min.
–4
4
0
4
0
0
4
Standard
C
R
VCC = 3.3 V
Max.
30
30
25
30
30
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns