16C6N4 RENESAS [Renesas Technology Corp], 16C6N4 Datasheet - Page 9

• Manufacturer Part Number: 16C6N4
• Description: Renesas MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ03B0003-0240
Under development
This document is under development and its contents are subject to change.
1.6 Pin Functions
Table 1.5 Pin Functions (1)
I: Input
NOTE:
Power supply
input
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
pins
Tables 1.5 to 1.7 list the Pin Functions.
Signal Name
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
Aug 25, 2006
O: Output
VCC1, VCC2,
VSS
AVCC, AVSS
_____________
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A19
A0/D0 to A7/D7
A1/D0 to A8/D7
_______
CS0 to CS3
_________ ______
WRL/WR
_________ ________
WRH/BHE
______
RD
ALE
__________
HOLD
__________
HLDA
________
RDY
Pin Name
page 9 of 88
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I/O: Input/Output
I/O Type
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.) to the VCC1
and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is
that VCC2 = VCC1
Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
The MCU is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1
to start up in microprocessor mode.
Switches the data bus in external memory space. The data bus
is 16-bit long when the this pin is held “L” and 8-bit long when
the this pin is held “H”. Set it to either one. Connect this pin to
VSS when single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as
the separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data
bus is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to
A7) by time-sharing when external 8-bit data bus are set as the
multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to
A8) by time-sharing when external 16-bit data bus are set as the
multiplexed bus.
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals
to specify an external space.
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
________
BHE, and WR can be switched by program.
• WRL, WRH, and RD are selected
• WR, BHE, and RD are selected
ALE is a signal to latch the address.
While the HOLD pin is held “L”, the MCU is placed in a hold
state.
In a hold state, HLDA outputs a “L” signal.
While applying a “L” signal to the RDY pin, the MCU is placed in
a wait state.
________
The WRL signal becomes “L” by writing data to an even address
The WRH signal becomes “L” by writing data to an odd address
in an external memory space.
The RD pin signal becomes “L” by reading data in an external
memory space.
______
The WR signal becomes “L” by writing data in an external
memory space.
The RD signal becomes “L” by reading data in an external
memory space.
The BHE signal becomes “L” by accessing an odd address.
Select WR, BHE, and RD for an external 8-bit data bus.
in an external memory space.
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(1)
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Description
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1. Overview
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