xc2234l-20f80l Infineon Technologies Corporation, xc2234l-20f80l Datasheet - Page 32

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xc2234l-20f80l

Manufacturer Part Number
xc2234l-20f80l
Description
Lim 16/32-bit Single-chip Microcontroller With 32-bit Performance Xc2000 Family / Econo Line
Manufacturer
Infineon Technologies Corporation
Datasheet
PRELIMINARY
Table 8
Address Area
ESFR area
XSFR area
Data SRAM (DSRAM)
Reserved for DSRAM
External memory area
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000
4) Several pipeline optimizations are not active within the external IO area.
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the
PSRAM with programmable size can be write-protected.
Data Sheet
external bus accesses.
XC223[04]L Memory Map (cont’d)
Start Loc. End Loc.
00’F000
00’E000
00’C800
00’8000
00’0000
H
H
H
H
H
00’F1FF
00’EFFF
00’DFFF
00’C7FF
00’7FFF
28
H
H
H
H
H
1)
Area Size
0.5 Kbytes
4 Kbytes
6 Kbytes
18 Kbytes
32 Kbytes
(cont’d)
XC2000 Family / Econo Line
2)
Functional Description
XC2230L, XC2234L
Notes
V1.0, 2010-12
H
to C0’FFFF
H
).

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