xc2234l-20f80l Infineon Technologies Corporation, xc2234l-20f80l Datasheet - Page 37

• Manufacturer Part Number: xc2234l-20f80l
• Description: Lim 16/32-bit Single-chip Microcontroller With 32-bit Performance Xc2000 Family / Econo Line
• Manufacturer: Infineon Technologies Corporation

XC2230L, XC2234L
XC2000 Family / Econo Line
PRELIMINARY
Functional Description
3.5
Interrupt System
The architecture of the XC223[04]L supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Using a standard interrupt service the current program execution is suspended and a
branch to the interrupt vector table is performed. With the PEC just one cycle is ‘stolen’
from the current CPU activity to perform the PEC service. A PEC service implies a single
byte or word data transfer between any two memory locations with an additional
increment of either the PEC source pointer, the destination pointer, or both. An individual
PEC transfer counter is implicitly decremented for each PEC service except when
performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source-related vector location. PEC services
are particularly well suited to supporting the transmission or reception of blocks of data.
The XC223[04]L has eight PEC channels, each with fast interrupt-driven data transfer
capabilities.
1)
With a minimum interrupt response time of 7/11
CPU clocks, the XC223[04]L can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 64 physical nodes with separate control register
containing an interrupt request flag, an interrupt enable flag and an interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger logic (ETL) a routing matrix and 4 output gating units
(OGU). The ETL features rising edge, falling edge, or both edges event detection. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XC223[04]L provides efficient mechanisms to identify and process exceptions or
error conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware
trap causes an immediate system reaction similar to a standard interrupt service
1) Depending if the jump cache is used or not.
Data Sheet
33
V1.0, 2010-12