IDT72V2103 IDT [Integrated Device Technology], IDT72V2103 Datasheet - Page 21

• Manufacturer Part Number: IDT72V2103
• Description: 3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
• Manufacturer: IDT [Integrated Device Technology]

BUS-MATCHING (IW, OW)
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate based on the word/
byte size boundary as defined by the selection of the widest input or output bus
width.
BIG-ENDIAN/LITTLE-ENDIAN (BE)
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when data is written into the FIFO in word format (x18) and read out
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected, then the most significant byte of the word written into the FIFO will be
read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. Refer
to Figure 4, Bus-Matching Byte Arrangement, for a diagram showing the byte
arrangement.
PROGRAMMABLE FLAG MODE (PFM)
Asynchronous Programmable flag timing mode. A HIGH on PFM will select
Synchronous Programmable flag timing mode. If asynchronous PAF/PAE
configuration is selected (PFM, LOW during MRS), the PAE is asserted LOW
on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-
HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-to-
HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D8 and D17 during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
programming of the offsets. (D8 becomes a valid bit). Additionally, output Q8 will
become a valid bit when performing a read of the offset register. IP mode is
selected during Master Reset by the state of the IP input pin. Interspersed Parity
control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.
OUTPUTS:
FULL FLAG (FF/IR)
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
The pins IW and OW are used to define the input and output bus widths.
During Master Reset, a LOW on BE will select Big-Endian operation. A
During Master Reset During Master Reset, a LOW on PFM will select
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
TM
NARROW BUS FIFO
TM
21
NARROW BUS FIFO
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO.
If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103
and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths
are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the
relevant timing information.
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,073 for
the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9
Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289
for the IDT72V2113. See Figure 9, Write Timing (FWFT Mode), for the relevant
timing information.
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
double register-buffered outputs.
EMPTY FLAG (EF/OR)
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
at the same time that the first word written to an empty FIFO appears valid on
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the
last word from the FIFO memory to the outputs. OR goes HIGH only with a true
read (RCLK with REN = LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until OR goes LOW
again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D-m) words are written
to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (131,072-m)
writes for the IDT72V2103 and (262,144-m) writes for the IDT72V2113. If both
x9 Input and x9 Output bus Widths are selected, (D-m) = (262,144-m) writes
for the IDT72V2103 and (524,288-m) writes for the IDT72V2113. The offset
“m” is the full offset value. The default setting for this value is stated in Table 2.
will go LOW after (131,073-m) writes for the IDT72V2103 and (262,145-m)
writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are
selected, the PAF will go LOW after (262,145-m) writes for the IDT72V2103 and
(524,289-m) writes for the IDT72V2113. The offset m is the full offset value. The
default setting for this value is stated in Table 2.
Standard and FWFT Mode), for the relevant timing information.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
The IR status not only measures the contents of the FIFO memory, but also
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES