IDT72V2103 IDT [Integrated Device Technology], IDT72V2103 Datasheet - Page 41

• Manufacturer Part Number: IDT72V2103
• Description: 3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
• Manufacturer: IDT [Integrated Device Technology]

TRST
SYSTEM INTERFACE PARAMETERS
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. 50pf loading on external output signals.
Data Output Hold
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
Data Output
Parameter
TDI/
TMS
TDO
TCK
Data Input
(1)
t
JTCKF
Symbol Test Conditions
t
t
DOH
DO
t
t
t
DH
DS
JRST
(1)
(1)
t
t
JTCKL
t
rise=3ns
fall=3ns
t
t
JTCKR
JRSR
t
t
TCK
DS
Min.
10
10
0
-
t
DH
IDT72V2103
IDT72V2113
Figure 31. Standard JTAG Timing
t
JTCKH
TM
Max. Units
20
NARROW BUS FIFO
-
-
-
ns
ns
ns
TM
41
NARROW BUS FIFO
(V
NOTE:
1. Guaranteed by design.
JTAG AC ELECTRICAL
CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
CC
= 3.3V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCK
JTCKH
JTCKL
JTCKR
JTCKF
JRST
JRSR
COMMERCIAL AND INDUSTRIAL
Conditions Min.
Test
t
DO
-
-
-
-
-
-
-
TEMPERATURE RANGES
100
40
40
50
50
-
-
TDO
Max. Units
5
5
-
-
-
-
-
(1)
(1)
6119 drw34
ns
ns
ns
ns
ns
ns
ns