IDT72V2103 IDT [Integrated Device Technology], IDT72V2103 Datasheet - Page 35

• Manufacturer Part Number: IDT72V2103
• Description: 3.3 VOLT HIGH-DENSITY SUPERSYNC II NARROW BUS FIFO
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9
Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input
and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113.
WCLK
WCLK
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
RCLK
RCLK
WEN
WEN
REN
REN
PAE
HF
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
[
n + 1 words in FIFO
D + 1
D/2 words in FIFO
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
n words in FIFO
2
]
words in FIFO
t
t
CLKH
CLKH
(1)
(2) ,
,
(2)
(3)
TM
t
t
ENS
NARROW BUS FIFO
ENS
t
t
CLKL
CLKL
TM
35
NARROW BUS FIFO
t
ENH
t
t
ENH
PAEA
t
HF
t
t
ENS
ENS
[
[
D + 1
n + 1 words in FIFO
n + 2 words in FIFO
D
2
2
+ 1
]
]
+ 1
words in FIFO
words in FIFO
t
PAEA
t
HF
(2) ,
(3)
(1)
,
COMMERCIAL AND INDUSTRIAL
(2)
n + 1 words in FIFO
[
TEMPERATURE RANGES
n words in FIFO
D + 1
D/2 words in FIFO
2
]
words in FIFO
(2) ,
6119 drw24
(1)
6119 drw25
,
(3)
(2)