IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 3

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
MAX
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
In FWFT mode, the first word written to an empty FIFO is clocked directly
For applications requiring more data storage capacity than a single FIFO
PAE and PAF can be programmed independently to switch at any point in
There are two possible timing modes of operation with these devices: IDT
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FIRST WORD FALL THROUGH/SERIAL INPUT
with complete independence. There are no restrictions on the frequency
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
(x36, x18, x9) DATA IN (D
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
Figure 1. Single Device Configuration Signal Flow Diagram
PARTIAL RESET (PRS)
INPUT WIDTH (IW)
LOAD (LD)
(FWFT/SI)
0
- D
n
)
MATCHING
TM
72V36100
72V36110
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
36-BIT FIFO
(BM)
BUS-
3
IDT
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
of RCLK can be used to read the offsets in parallel from Q
serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
MASTER RESET (MRS)
For serial programming, SEN together with LD on each rising edge of
During Master Reset (MRS) the following events occur: the read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
It is also possible to select the timing mode of the PAE (Programmable Almost-
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
OUTPUT WIDTH (OW)
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
(x36, x18, x9) DATA OUT (Q
OUTPUT ENABLE (OE)
n
. REN together with LD on each rising edge
COMMERCIAL AND INDUSTRIAL
0
TEMPERATURE RANGES
- Q
n
n
)
regardless of whether
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