A400CB10RC AMD [Advanced Micro Devices], A400CB10RC Datasheet - Page 16

• Manufacturer Part Number: A400CB10RC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against in-
advertent writes (refer to
14
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 2. Temporary Sector Unprotect Operation
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
Table 5 on page 18
RESET# = V
RESET# = V
(Note 1)
(Note 2)
START
ID
IH
for command
D A T A
Am29SL400C
S H E E T
definitions). In addition, the following hardware data protec-
tion measures prevent accidental erasure or programming,
which might otherwise be caused by spurious system level
signals during V
from system noise.
Low V
When V
write cycles. This protects data during V
power-down. The command register and all internal pro-
gram/erase circuits are disabled, and the device resets. Sub-
sequent writes are ignored until V
The system must provide the proper signals to the control
pins to prevent unintentional writes when V
V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
CE# = V
WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
vice does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to reading
array data on power-up.
LKO
.
CC
CC
IH
Write Inhibit
is less than V
or WE# = V
CC
IL
power-up and power-down transitions, or
and OE# = V
IH
LKO
. To initiate a write cycle, CE# and
Am29SL400C_00_A6 January 23, 2007
, the device does not accept any
IH
CC
during power up, the de-
is greater than V
CC
CC
power-up and
is greater than
LKO
IL
.
,