A400CB10RC AMD [Advanced Micro Devices], A400CB10RC Datasheet - Page 18

• Manufacturer Part Number: A400CB10RC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command se-
quence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the pro-
gram address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time.
on page 18
quence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the
two-cycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data
00h. Addresses are don’t cares. The device then returns to
reading array data.
Figure 3‚ on page 16
operation. See
parameters, and
Note: See
16
Increment Address
Table 5
shows the requirements for the command se-
Figure 3. Program Operation
Erase/Program Operations‚ on page 30
in progress
Embedded
for program command sequence.
Figure 17‚ on page 31
algorithm
Program
illustrates the algorithm for the program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
for timing diagrams.
Yes
Yes
D A T A
No
Table 5
Am29SL400C
for
S H E E T
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase com-
mand sequence is initiated by writing two unlock cycles, fol-
lowed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to pro-
vide any controls or timings during these operations.
on page 18
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates the
operation. The Chip Erase command sequence should be
reinitiated once the device has returned to reading array
data, to ensure data integrity The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. See
mation on these status bits. When the Embedded Erase al-
gorithm is complete, the device returns to reading array data
and addresses are no longer latched.
Figure 4‚ on page 17
operation. See
parameters, and to Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command.
shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm au-
tomatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not re-
quired to provide any controls or timings during these opera-
tions.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period, addi-
tional sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sec-
tor to all sectors. The time between these additional cycles
must be less than 50 µs, otherwise the last address and
command might not be accepted, and erasure may begin. It
is recommended that processor interrupts be disabled dur-
ing this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other than
Sector Erase or Erase Suspend during the time-out pe-
riod resets the device to reading array data. The system
must rewrite the command sequence and any additional
sector addresses and commands.
shows the address and data requirements for
Write Operation Status‚ on page 19
Erase/Program Operations‚ on page 30
illustrates the algorithm for the erase
Am29SL400C_00_A6 January 23, 2007
Table 5 on page 18
for infor-
Table 5
for