lxt971a Intel Corporation, lxt971a Datasheet - Page 47

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lxt971a

Manufacturer Part Number
lxt971a
Description
3.3v Dual-speed Fast Ethernet Phy Transceiver
Manufacturer
Intel Corporation
Datasheet

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Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 12. BSR Mode of Operation
Table 13. Supported JTAG Instructions
Table 14. Device ID Register
EXTEST
IDCODE
SAMPLE
HIGHZ
CLAMP
BYPASS
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC ID is FE
2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the
Mode
Version
(1111 1110), which becomes 111 1110.
Jedec continuation characters.
1
2
3
4
XXXX
31:28
Name
2
Part ID (hex)
System Function
1111 1111 1110 1000
1111 1111 1111 1000
1111 1111 1111 1110
1111 1111 1100 1111
1111 1111 1110 1111
1111 1111 1111 1111
Description
27:12
03CB
Capture
Update
Shift
Code
Jedec Continuation Characters
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
External Test
ID Code Inspection
Sample Boundary
Force Float
Control Boundary to 1/0
Bypass Scan
Description
0000
11:8
Test
Normal
Normal
Normal
Test
Normal
Mode
JEDEC ID
111 1110
7:1
BSR
ID REG
BSR
Bypass
Bypass
Bypass
1
Data Register
Reserved
0
1
47

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