lxt971a Intel Corporation, lxt971a Datasheet - Page 61

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lxt971a

Manufacturer Part Number
lxt971a
Description
3.3v Dual-speed Fast Ethernet Phy Transceiver
Manufacturer
Intel Corporation
Datasheet

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5.2
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Figure 28. 100BASE-TX Receive Timing - 4B Mode
Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode
Timing Diagrams
RXD<3:0>, RX_DV, RX_ER setup
to RX_CLK High
RXD<3:0>, RX_DV, RX_ER hold
from RX_CLK High
CRS asserted to RXD<3:0>, RX_DV
Receive start of “J” to CRS asserted
Receive start of “T” to CRS de-asserted
Receive start of “J” to COL asserted
Receive start of “T” to COL de-asserted
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production
2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate.
testing.
100BASE-T bit time = 10
RXD<3:0>
Parameter
RX_CLK
RX_DV
TPFI
CRS
COL
-8
0ns
s or 10 ns.
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Sym
t4
t6
t1
t2
t3
t4
t5
t6
t7
Min
10
10
12
10
16
17
3
t3
Typ
1
250ns
Max
16
17
22
20
5
t5
t7
t1
Units
t2
BT
BT
BT
BT
BT
ns
ns
2
Test Conditions
61

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