em78p210n ELAN Microelectronics Corp, em78p210n Datasheet - Page 21

• Manufacturer Part Number: em78p210n
• Description: 8-bit Microcontroller With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.2) 04.22.2008
(This specification is subject to change without further notice)
6.2.22 Bank 1-RE (WDT Control Register)
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer
Bits 6, 1:
Bit 5 (PSWE): Prescaler enable bit for WDT
Bit 4 ~ Bit 2 (PSW2 ~ PSW0): WDT prescaler bits
Bit 0 (CMPIE): CMPIF interrupt enable bit
WDTE
PSW2
Bit 7
0
0
0
0
1
1
1
1
Bank 1-RE <0> register is both readable and writable
Individual interrupt is enabled by setting its associated control bit in the
Bank 1-RF <0 > to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Figure 6-8 (Interrupt Input Circuit) under Section 6.6
(Interrupt).
PSW1
Bit 6
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable.
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit 4~Bit 2
0
not used, fixed to 0 all the time
0
0
1
1
0
0
1
1
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter an
interrupt vector or to enter next instruction, the CMPIE bit must be set
to “Enable“. But actually the comparator output must be read to latch
the status first. Then the output of the comparator is compared to this
latch to produce the information of output status change.
PSWE
Bit 5
PSW0
0
1
0
1
0
1
0
1
PSW2
Bit 4
WDT Rate
1:256
1:2
1:4
1:8
1:16
1:32
1:64
1:128
NOTE
PSW1
Bit 3
8-Bit Microcontroller with OTP ROM
PSW0
Bit 2
Bit 1
0
EM78P210N
CMPIE
Bit 0
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