bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 129

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
The processor writes JAT_CR register at power-up, activating the JAUTO and JCENTER bits to initialize the
jitter attenuator elastic store. The processor can maximize jitter tolerance by repeating JCENTER after
recovering from an error [CKERR; addr 006] on the JAT input clock reference. JAT elastic store automatically
recenters upon detection of an elastic store limit error [JERR; addr 006].
JEN
JFREE
JDIR
N8370DSE
002— Jitter Attenuator Configuration (JAT_CR)
JEN
7
Jitter Attenuator Enable—JCLK and CLADO are locked to the timing reference selected. The
reference frequency can operate at T1 or E1 line rates, or at any rate supported by the clock
rate adapter. See RSCALE[2:0] [addr 092] for selecting the timing reference frequency.
Free-Running JCLK and CLADO—Disables both CLADI and JAT phase detectors in the
clock rate adapter, which forces the Numerical Controlled Oscillator (NCO) to free-run based
on the 10 MHz REFCKI input clock accuracy. When JFREE is active, JEN and JDIR select
jitter attenuator direction.
Select JAT Direction—Applicable only when the jitter attenuator is enabled (see JEN
description). JAT elastic store is placed in either the receive or transmit direction, and JCLK is
placed on RCKO or TCKO pin according to JDIR selection.
NOTE:
JFREE
CEN
0
0
0
0
0
1
1
1
6
JCLK always operates at T1 or E1 line rate selected by [T1/E1N; addr 001].
JEN
0
1
1
1
1
0
1
1
JDIR
JFREE
5
1
1
1
0
0
0
0
0
0 = normal (closed loop) CLAD/JAT operation
1 = free run (open loop) NCO operation
0 = JAT in TX direction, JCLK output on TCKO
1 = JAT in RX direction, JCLK output on RCKO
JDIR
X
X
0
1
0
1
0
1
JAUTO
4
Conexant
REFCKI—Free running 10 MHz clock
REFCKI—Free running 10 MHz clock with transmit JAT
REFCKI—Free running 10 MHz clock with receive JAT
TXCLK—TCKI or ACKI per [AISCLK; addr 068]
RXCLK—RPLL or RCKI per [RDIGI; addr 020]
CLADI—System clock, bypass JAT elastic store
CLADI—System clock with transmit JAT
CLADI—System clock with receive JAT
JCENTER
3
CLADO/JCLK Reference
JSIZE[2]
2
3.2 Global Control and Status Registers
JSIZE[1]
1
3.0 Registers
JSIZE[0]
0
3-11