bt8375kpf Conexant Systems, Inc., bt8375kpf Datasheet - Page 70

• Manufacturer Part Number: bt8375kpf
• Description: Single Chip Transceivers For T1/e1 And Integrated Service Digital Network Isdn Primary Rate Interfaces Systems
• Manufacturer: Conexant Systems, Inc.

2.0 Circuit Description
2.6 Clock Rate Adapter
2-42
frequency can operate at T1 or E1 line rates, or at any rate supported by the clock
rate adapter. See RSCALE[2:0] [addr 092] to select timing reference frequency.
See
Table 2-6. JCLK/CLADO Timing Reference
as listed in
Table 2-7. Jitter Generation Requirements
register [CLAD_CR; addr 090], the Clock Rate Adapter Frequency Select
[CSEL; addr 091], and the Clock Rate Adapter Phase Detector Scale Factor
[CPHASE; addr 092].
CLAD input timing reference is determined by the JEN and JFREE bits
(addr 002).
timing reference is selected using CLADI[1:0] in the Clock Input Mux register
[CMUX; addr 01A]. The input timing reference can consist of the Clock Rate
Adapter Input Pin (CLADI); the Receive Clock Output (RCKO, prior to the
output buffer); the Transmit Clock Input Pin (TCKI); or the Transmit System Bus
Clock Input Pin (TSBCKI). (See
CEN
NOTE(S):
1. JCLK always operates at T1 or E1 line rate selected by [T1/E1N; addr 001]
0
0
0
0
0
1
1
1
JCLK and CLADO are locked to the selected timing reference. The reference
CLAD output jitter meets jitter generation requirements of AT&T TR62411,
CLAD modes are selected using the Clock Rate Adapter Configuration
If the CLAD Phase Detector (CPHASE) is disabled [CEN; addr 090], the
If the CLAD Phase Detector is enabled [CEN; addr 090], the CLAD input
Table 2-6
None (Broadband)
10 Hz to 40 kHz
8 kHz to 40 kHz
JEN
Filter Applied
10 Hz to 8 kHz
0
1
1
1
1
0
1
1
Table
for the JCLK/CLADO timing reference.
JFREE
2-7.
1
1
1
0
0
0
0
0
Conexant
JDIR
X
X
0
1
0
1
0
1
REFCKI—Free running 10 MHz clock
REFCKI—Free running 10 MHz clock with transmit JAT
REFCKI—Free running 10 MHz clock with receive JAT
TXCLK—TCKI or ACKI per [AISCLK; addr 068]
RXCLK—RPLL or RCKI per [RDIGI; addr 020]
CLADI—System clock bypass JAT elastic store
CLADI—System clock with transmit JAT
CLADI—System clock with receive JAT
Figures 2-21
Maximum Output Jitter
Fully Integrated T1/E1 Framer and Line Interface
0.025 UI peak-peak
0.025UI peak-peak
0.05 UI peak-peak
0.02UI peak-peak
CLADO/JCLK Reference
and
2-22
for more details.)
Bt8370/8375/8376
Measured
.015 UI
.015 UI
.015 UI
.015 UI
N8370DSE