ml6692 Microsemi Corporation, ml6692 Datasheet
ml6692
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ml6692 Summary of contents
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... GENERAL DESCRIPTION The ML6692 implements the complete physical layer of the Fast Ethernet 100BASE-TX standard. The ML6692 interfaces to the controller through the standard-compliant Media Independent Interface (MII). The ML6692 functionality includes auto-negotiation, 4B/5B encoding/ decoding, Stream Cipher scrambling/descrambling, 125MHz clock recovery/generation, receive adaptive equalization, baseline wander correction, and MLT-3/ 10BASE-T transmitter ...
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... ML6692 PIN CONFIGURATION DGND1 DGND2 DGND3 2 ML6692 52-Pin PLCC (Q52 TXER 8 TXCLK 9 RXD3 10 11 RXD2 12 DVCC1 13 RXD1 14 15 RXD0 16 RXCLK 17 CRS 18 COL TOP VIEW 46 CMREF 45 TPINP 44 TPINN LINK100 ...
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... DGND2B 10 RXD0 11 RXCLK 12 CRS 13 COL 14 DGND3A 15 DGND3B 16 ML6692 64-Pin TQFP (H64-10 TOP VIEW ML6692 48 DUPLEX 47 CMREF 46 TPINP 45 TPINN LINK100 44 43 AVCC2 42 AGND2A 41 AGND2B 40 TPOUTP 39 TPOUTN ...
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... COL is low when the ML6692 operates in either full duplex, or loopback modes. 20 (15, 16) DGND3 Digital ground. 21 (17) RXDV Receive data valid TTL output. This output goes high when the ML6692 is receiving a data packet. RXDV should be sampled synchronously with RXCLK’s rising edge. 22 (18) DVCC2 Digital +5V power supply. 23 (19) RXER Receive error TTL output ...
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... MDIO MII Management Interface data TTL input/output. Serial data are written to and read from the ML6692’s management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Data output should be sampled synchronously with MDC's rising edge. 26 (22, 23) DGND4 Digital ground ...
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... DUPLEX can be used to disable the 10BASE-T transceiver’s receive and collision outputs to the controller during auto-negotiation. 48, 49 (50, 51) 10BTTXINN/P 10BASE-T transmit waveform inputs. The ML6692 presents a linear copy of the input at 10BTTXINP/N to the TPOUTP/N outputs when the ML6692 functions in 10BASE-T mode. Signals presented to these pins must be centered at V amplitude of ± ...
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... All GND pins must be within 0.1V of each other Ambient temperature .............................. 0ºC to 70°C A RGMSET .................................................... 9.53k ± 1% RTSET ........................................................ 2.49k Receive transformer insertion loss ...................... <–0.5dB CONDITIONS RGMSET = 9.53k RTSET = 2.49k Note 200 200 ML6692 ) JA ± 1% MIN TYP MAX UNITS V – 1. –3.0 3.0 V 10.0k +10 µ ...
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... ML6692 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TRANSMITTER (Continuied) X TPOUTP/N Differential Output ERR Current Error X TPOUTP/N 100BASE-X Output CMP100 Current Compliance Error V TPOUTP/N 10BASE-T Output OCM10 Voltage Compliance Range V 10BTTXNN/P Input ICM10 Common-Mode Voltage Range POWER SUPPLY CURRENT I Supply Current, 100BASE-TX CC100 Operation, Transmitting ...
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... RXCLK 90%-10% Fall Time RPCF CONDITIONS MIN Notes 5, 6; for any legal code sequence Notes 5, 6; for any legal –0.5 code sequence Notes 4, 6 – 0.5 Note 6 Notes 6, 7 Note 8 Note 9 Note 10 25MHz frequency –100 ML6692 TYP MAX UNITS V – 1. 3.0 5.0 ns 0.5 ns 0.5 ns 300 1400 ps ...
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... ML6692 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MDC-MDIO (MII MANAGEMENT INTERFACE) t Write Setup Time, MDIO Data SPWS Valid to MDC Rising Edge 1.4V Point t Write Hold Time, MDIO Data SPWH Valid After MDC Rising Edge 1.4V Point t Read Setup Time, MDIO Data SPRS Valid to MDC Rising Edge 1 ...
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... Figure 3. MII Receive Timing MDC MDIO t SPWS Figure 4. MII Management Interface Write Timing MDC t SPRS MDIO Figure 5. MII Management Interface Read Timing 2 Figure TPWH TPWL t TPH t RPCR t RCH t SPWH t CPER t SPRH t t CPW CPW ML6692 t RPCF 11 ...
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... TXCLK rising edge, and the H symbol appears at least once in place of a valid symbol in the current packet. With no data at TXD<3:0> or with the ML6692 in isolate mode (MII Management register bit 0.10 set to a 1), scrambled idle appears at TPOUTP/N. Auto Negotiation and Fast Link Pulses (FLPs) During the auto negotiation process, the transmitter produces nominal 5V fast link pulses (FLP’ ...
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... T4EN high to deactivate external 10BASE-T and 100BASE-T4 transceivers. If the 100BASE-T4 transceiver detects activity, it will drive the ML6692’s T4FAIL pin high and the ML6692 will place its receiver and transmitter in an idle state, and will drive 10BTLNKEN high. ...
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... ML6692 automatically generates the address at EDIN and the clock at ECLK to read out the 16 configuration bits. The EEPROM generates the configuration bit stream at EDOUT, synchronized with ECLK. Interface timing is shown in Figure important to note that the ML6692 expects LSBs first, whereas the 93LC46 shifts MSBs out EDIN MODE ...
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... ML6692 from MII 0 = normal operation 1 = restart auto negotiation 0 = normal operation 1 = Full duplex select, auto negotiation disabled 0 = Half duplex select, auto negotiation disabled 1 = enable COL signal test 0 = normal operation Table 2 ...
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... ML6692 MII MANAGEMENT INTERFACE REGISTERS BIT(S) NAME 1.15 100BASE-T4 1.14 100BASE-TX full duplex 1.13 100BASE-TX half duplex 1.12 10Mb/s full duplex 1.11 10BASE-T (half duplex) 1.10 – 1.6 Not Used 1.5 Auto negotiation compl. 1.4 Not Used 1.3 Auto negotiation ability 1.2 Link status 1.1 Not Used 1.0 Extended capability BIT(S) NAME 4.15 Next Page 4 ...
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... NOT received 0 = link partner has NO auto negotiation capability Table 6. Expansion Register ML6692 R/W DEFAULT R/W X ...
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... ML6692 VCC GND VCC TX+ FD GND LTP TXC RPOL TXD COL TXE CS0 RTX INTERFACE 7-WIRE 18 DUPLEX 10BTTXINN 10BTTXINP 10BTRCV 10BTLINKEN AVCC1 TXCLKIN AGND1 TXD3 TXD2 TXD1 TXD0 TXEN Table 8. 10/100 BASE-T Application Circuit ECLK SEL10FD/ SEL10HD EDIN T4FAIL T4EN DGND5 ...
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... ML2653 (10BASE-T PHY) and ML6692 (100BASE-TX PHY). The inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6692, and improves the Bit Error Rate (BER) performance of the board. We ML6692 PARTS LIST COMPONENT ...
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... ML6692 PHYSICAL DIMENSIONS 0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 1 PIN 0.020 BSC (0.50 BSC) 20 inches (millimeters) Package: Q52 52-Pin PLCC 0.750 - 0.754 0.785 - 0.795 40 (19.05 - 19.15) (19 ...
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... DS6692-02 inches (millimeters) TEMPERATURE RANGE 0°C - 70°C 0°C - 70° registered trademark of Micro Linear Corporation. All other trademarks are the ML6692 PACKAGE 64 Pin Thin Quad Flat Pack (TQFP) 52 Pin Plastic Leaded Chip Carrier (PLCC) 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www ...