ml6692 Microsemi Corporation, ml6692 Datasheet - Page 4

• Manufacturer Part Number: ml6692
• Description: 100base-tx Physical Layer With
• Manufacturer: Microsemi Corporation

ML6692
PIN DESCRIPTION
PIN
1 (56)
2 (57, 58)
3, 4, 5, 6,
(59, 60, 61, 62)
7 (63)
8 (64)
9 (1)
10, 12, 14, 16
(2, 5, 8, 11)
11 (3, 4)
13 (6, 7)
15 (9, 10)
17 (12)
18 (13)
19 (14)
20 (15, 16)
21 (17)
22 (18)
23 (19)
24 (20)
4
NAME
TXCLKIN
AGND1
TXD<3:0>
TXEN
TXER
TXCLK
RXD<3:0>
DGND1
DVCC1
DGND2
RXCLK
CRS
COL
DGND3
RXDV
DVCC2
RXER
MDC
(Pin Numbers for TQFP package in parentheses)
FUNCTION
transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at
TTL or CMOS levels.
Analog ground.
Transmit data TTL inputs. TXD<3:0> inputs accept TX data from the MII. Data
appearing at TXD<3:0> are clocked into the ML6692 on the rising edge of TXCLK.
Transmit enable TTL input. Driving this input high indicates to the ML6692 that transmit
data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK.
Transmit error TTL input. Driving this pin high with TXEN also high causes the part to
continuously transmit scrambled H symbols. When TXEN is low, TXER has no effect.
Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz
TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6692 on the rising
edge of this clock.
Receive data TTL outputs. RXD<3:0> outputs are valid on RXCLK’s rising edge.
Digital ground.
Digital ground.
Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the
internal 125MHz bit clock recovered from the signal received at TPINP/N. Receive data
at RXD<3:0> changes on the falling edges and should be sampled on the rising edges of
this clock. RXCLK is phase aligned to TXCLKIN when the 100BASE-TX signal is not
present at TPINP/N.
Carrier Sense TTL output. For 100Mbps operation in standard mode, CRS goes high in the
presennon-idle signals at TPINP/N, or when the ML6692 is transmitting. CRS goes low when
there is no transmit activity and receive is idle. For 100 Mbps operation in repeater mode
or half duplex mode, CRS goes high in the presence of non-idle signals at TPINP/N only.
Collision Detected TTL output. For 100 Mbps operation COL goes high upon detection of
a collision on the network, and remains high as long as the collision condition persists.
COL is low when the ML6692 operates in either full duplex, or loopback modes.
Digital ground.
Receive data valid TTL output. This output goes high when the ML6692 is receiving a
data packet. RXDV should be sampled synchronously with RXCLK’s rising edge.
Receive error TTL output. This output goes high to indicate error or invalid symbols
within a packet, or corrupted idle between packets. RXER should be sampled
synchronously with RXCLK’s rising edge.
MII Management Interface clock TTL input. A clock at this pin clocks serial data into or
out of the ML6692’s MII management registers through the MDIO pin. The maximum clock
frequency at MDC is 2.5MHz.
Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal
Digital +5V power supply.
Digital +5V power supply.