ml6692 Microsemi Corporation, ml6692 Datasheet - Page 12

• Manufacturer Part Number: ml6692
• Description: 100base-tx Physical Layer With
• Manufacturer: Microsemi Corporation

ML6692
FUNCTIONAL DESCRIPTION
TRANSMIT SECTION
100BASE-TX Operation
The transmitter includes everything necessary to accept
4-bit data nibbles clocked in at 25MHz at the MII and
output scrambled, 5-bit encoded MLT-3 signals into
twisted pair at 100Mbps. The on-chip transmit PLL
converts a 25MHz TTL-level clock at TXCLKIN to an
internal 125MHz bit clock. TXCLK from the ML6692
clocks transmit data from the MAC into the ML6692’s
TXD<3:0> input pins upon assertion of TXEN. Data from
the TXD<3:0> inputs are 5-bit encoded, scrambled, and
converted from parallel to serial form at the 125MHz
clock rate. The serial transmit data is converted to MLT-3
3-level code and driven differentially out of the TPOUTP
and TPOUTN pins at nominal ±2V levels with the proper
loads. The transmitter is designed to drive a center-tapped
transformer with a 2:1 winding ratio, so a differential 400ý
load is used on the transformer primary to properly
terminate the 100
secondary. The transformer’s center tap must be tied to
V
current in 100BASE-TX mode and ±60mA in fast link pulse
and 10BASE-T modes. Using a 1:1 transformer would have
required twice the output current and increased the on-
chip power dissipation. An external 2.49k , 1% resistor at
the RTSET pin creates the correct output levels at
TPOUTP/N.
Driving TXER high when TXEN is high causes the H
symbol (00100) to appear in scrambled MLT-3 form at
TPOUTP/N. The media access controller asserts TXER
synchronously with TXCLK rising edge, and the H symbol
appears at least once in place of a valid symbol in the
current packet.
With no data at TXD<3:0> or with the ML6692 in isolate
mode (MII Management register bit 0.10 set to a 1),
scrambled idle appears at TPOUTP/N.
Auto Negotiation and Fast Link Pulses (FLPs)
During the auto negotiation process, the transmitter
produces nominal 5V fast link pulses (FLP’s) at
TPOUTP/N (2.5V after 2:1 transformer). When the auto
negotiation process is complete, the transmitter either
switches over to 100BASE-TX mode, activates the
10BTTXINP/N inputs for 10BASE-T operation with an
external 10BASE-T transceiver, or enables a 100BASE-T4
PMA and powers down the on-chip transmitter.
10BASE-T
In 10BASE-T mode, the transmitter acts as a linear buffer
with a gain of 10. 10BASE-T inputs (Manchester data and
normal link pulses) at 10BTTXINP/N appear as full-swing
signals at TPOUTP/N in this mode. Inputs to the
10BTTXINP/N pins should have a nominal ±0.25V
differential amplitude and a common-mode voltage of
V
12
CC
CC
. A 2:1 transformer allows using a ±20mA output
/2, and should also be waveshaped or filtered to meet
cable and termination on the
the 10BASE-T harmonic content requirements. The
ML6692 does not provide any 10BASE-T transmit filtering.
The ML2653 10BASE-T physical interface chip provides a
waveshaped 10BASE-T output and may be used with a
resistive load network for a simple 2-chip 10/100 solution
with the ML6692. The ML2653 interfaces to a controller
through it’s “7-wire” interface.
RECEIVE SECTION
100BASE-TX Operation
The receiver includes all necessary functions for
converting 3-level MLT-3 signals from the twisted-pair
media to 4-bit data nibbles at RXD<3:0> with extracted
clock at RXCLK. The adaptive equalizer compensates for
cable distortion and attenuation, corrects for DC baseline
wander, and converts the MLT-3 signal to 2-level NRZ.
The receive PLL extracts clock from the equalized signal,
providing additional jitter attenuation, and clocks the
signal through the serial to parallel converter. The
resulting 5-bit nibbles are descrambled, aligned and
decoded, and appear at RXD<3:0>. The ML6692 asserts
RXDV when it’s ready to present properly decoded
receive data at RXD<3:0>. The extracted clock appears at
RXCLK. Resistor RGMSET sets internal time constants
controlling the adaptive equalizer’s transfer function.
RGMSET must be set to 9.53k
The receiver will assert RXER high if it detects code errors
in the receive data packet, or if the idle symbols between
packets are corrupted.
COL goes high to indicate simultaneous 100BASE-TX
receive and transmit activity (a collision). CRS goes high
whenever there is either receive or transmit activity in the
ML6692’s “station” mode (the default mode; see
Initialization Interface section below for more
information). In the ML6692’s “repeater” mode, CRS goes
high only when there is receive activity.
Auto Negotiation
The 100BASE-TX signal detect circuit in the adaptive
equalizer ignores fast and normal link pulses, and will not
pass them on to the rest of the receive channel. Instead,
FLPs (and NLPs) are recognized and processed by the auto
negotiation logic. When the auto negotiation process is
complete, either the adaptive EQ and the rest of the
100BASE-TX receive path remain active for 100BASE-TX
reception, all the ML6692’s receive circuitry is disabled
and the external 10BASE-T transceiver is enabled (if it
exists), or all the ML6692's 10BASE-T and 100BASE-TX
functionality is disabled and an external 100BASE-T4
PMA is enabled. In 10BASE-T or 100BASE-T4 modes, the
ML6692 RXD<3:0>, RXC, RXER, RXDV, COL and CRS MII
outputs are in high impedance state. See the next section
for more information on auto negotiation.
Proper connection of the TPIN pins, magnetics, and cable
is necessary for proper auto negotiation since the ML6692
(1%).