ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 17

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ml6652

Manufacturer Part Number
ml6652
Description
10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
Manufacturer
Sirenza Microdevices
Datasheet

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17
Note: In transparent mode the ML6652 does not generate
information. It only takes the information from the link
partner on one side (without adding or remove any
information) and it translates it to the language of the link
partner of other side.
This mode is for use in networks that have Auto-
Negotiation capabilities on both copper and fiber sides.
The ML6652 follows the demands of the far end link
partners during the network Auto-Negotiation. Link
Integrity Warning (LIW) cannot be enabled in this mode.
6) Special case for the Non-Transparent Mode:
If the Fiber Optic Link Partner is Auto-Negotiation capable
the ML6652 will allow the fiber optic link partner to Auto-
Negotiate through the ML6652 to the twisted pair link
partner. In this special case the non-transparent mode acts
in the same way as the transparent mode. This is because
the self-generation of FLP bursts is suppressed by the
presence of the FLP bursts from the fiber link partner.
The ML6652 can be configured in two general ways:
1) Through the management interface, pins 16 (MDIO)
OPERATING MODES
TRANSPARENT or NON-TRANSPARENT Mode of
operation. Transparent Mode is the default mode of
operation for the ML6652 when DUPLEX input is VCC/
2. In this mode, the control circuit implements the
state diagrams of the Auto-Negotiation sub-layer
defined in clause 5 of TIA/EIA-785 standard. In general
the enabled Physical Media Attachment (PMA) at the
fiber optic output is the equivalent to the technology
detected at the twisted pair input and the enabled
PMA at the twisted pair output is the equivalent to the
technology detected at the fiber optic input. Of
course system Auto-Negotiation causes both paths to
the greatest common denominator. The system
chooses the greatest common denominator in the
following order least to greatest:
a)
b)
c)
d)
The ML6652 operates in this mode when all of the
following three conditions are met:
a)
b)
c)
and 17 (MDC), all of the registers can be changed
after power-up. The management interface settings
override any power-up register settings.
equivalent Reg. 30 settings) AND
AND
by SPEED input at VCC/2 or by bits in
management register 30.
Half DUPLEX, 10Mbs
Full DUPLEX, 10Mbs
Half DUPLEX, 100Mbs
Full DUPLEX, 100Mbs
Duplex input is a VCC or a 0 Volts (or the
Twisted Pair Link is Auto-Negotiation capable
Both 10Mbps and 100Mbps operation are enabled
January 2004
2) Through configuration and control pins
Note: These pins are typically read a few microseconds
after power-up, if they are tied to supplies that do not
track the ML6652 power improper results may occur. To
reduce the parts count, pins Pin 7 (PECLTP), Pin 8
(PECLQU), Pin 4 (AD4LIW), Pin 5 (AD 32) and Pin 6
(AD10) may be supplies from a common 20kΩ resistor
tree as shown on our evaluation boards schematics
Final Datasheet
a)
ii) Select interface configurations
iii) Special modes
iv) And read control information
Note: Pins 4 AD4LIW and 40 BCKPLINK are both
shared between a power-up read and a later control
function and thus appear in both lists. Pin 4 AD4LIW
is read and the condition latched to set register 30 bit
12 subsequently it is used as an unlatched address
pin. Pin 40 BCKPLINK is read and the condition
latched to set register 28 bit 1, subsequently it is used
as an output to drive a second ML6652 to provide
back up link.
a)
i)
(1) Both fiber and copper
(1) Power Down Mode
(2) Loopback Test Modes
(3) Transmitter Output Off Mode:
(4) Backup Link Mode (Pin 40)
appropriate registers are set: (but with a limited
sub-set of the control afforded by the
management control registers.)
i)
ii) Pin 8 (PECLQU)
iii) Pin 25 (DUPLEX)
iv) Pin 27 (SPEED)
v)
vi) Pin 40 (BCKLINK)
All internal registers may be used to:
At power up the following pins are read and the
(1) FORCED 10Mbps only mode,
(2) FORCED 100Mbps only mode,
(3) NON-TRANSPARENT Half Duplex only
(4) NON-TRANSPARENT Full and Half
(5) TRANSPARENT 10/100Mbps with Auto-
Set operating modes,
Pin 7 (PECLTP)
Pin 4 (AD4LIW)
Duplex with Auto-Negotiation
Negotiation
DS6652-F-02
ML6652

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