ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 19

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

19
resistor is connected to ground and a 1nf capacitor is
connected to IOUT to determine the peaking current
waveform. If peaking is not implemented, IOUT# should
be connected directly to VCC.
The preferred mode of operation is PECL/LVPECL
differential outputs. The default mode of operation is set
by PECLQU (pin 8).
POWER DOWN MODE
Enabled by setting PWRDWN# (pin 24) all circuits are
powered down, all internal control logic is reset, and
output currents are turned off. 3µs to 8µs after the low to
high transition (trailing edge) of PWRDWN# the logic
levels at configuration input pins DUPLEX (pin 25), SPEED
(pin 27), PECLTP (pin 7), PECLQU (pin 8), AD4LIW (pin
4), and BCKLINK (Pin 40) are latched in the ML6652 and
all management control register bits are reset.
Enabled by setting management register bit <31.15> high,
all circuits are powered down, (except the management
interface) all internal control logic is reset and output
currents are turned off. Control input pins DUPLEX,
SPEED, PECLTP, PECLQU, and AD4LIW are not relatched
and management control register bits are not reset.
LOOPBACK MODE
Loopback of both the twisted pair inputs and fiber optic
inputs to their respective differential outputs is possible
with the ML6652.
Enabled by setting management register bit <31.12>, the
twisted pair input signal at TPINP (pin 10) and TPINN (pin
11) are looped back to TPOUTP (pin 1) and TPOUTN (pin
3). The clock/data PLL is normally included in the
loopback path. Setting management register bit <31.10>
PLLPBK# active (low) removes the PLL from the loopback
path.
Enabled by setting management register bit <31.11>, the
fiber input signal at FOINP (pin 33) and FOINN (pin 32)
are looped back to IOUT (pin 21) and IOUT# (pin 22).
The clock/data PLL is normally included in the loopback
path. Setting management register bit <31.10>
PLLLPBK# active (low) removes the PLL from the
loopback path.
SCRAMBLER/DESCRAMBLER
The scrambler and descrambler functions are enabled in
the 100Mbps signal paths by setting the management
register bit <30.1>. The scrambler and descrambler are
compliant with the Fiber Distributed Data Interface
Twisted Pair-Physical Media Dependent (FDDI TP-PMD)
standard ANSI X3T9.5 PMD/312. Setting management
register bit <30.0> forces the 11-bit scrambler register
state to 00000000011(bin). Clearing <30.0> returns the
scrambler register to normal operation.
OPERATING MODES
January 2004
The default state for <30.0> is logic 0 or normal scrambler
operation.
OUTPUT OFF MODE
Either the twisted pair outputs or the fiber optic outputs
can be turned off by a control input pin or a management
register bit. Disabling either differential output results in
the output pair being turned off and the data output pins
entering a high impedance state.
The twisted pair differential output TPOUTP and TPOUTN
is turned off by setting TPOUTOFF# low or management
register bit <31.13> high. The fiber optic differential
output IOUT and IOUT# is turned off by setting
FOOUTOFF# low or management register bit <31.14>
high.
BACKUP LINK MODE
A backup link mode of operation is available when the
primary fiber optic link is down. It can only be enabled
in the 100Mbps only, non-loopback mode of operation
configured by SPEED (pin 27) input level set to VCC. Two
ML6652 devices are required to implement the backup
link mode of operation with one driving the primary fiber
optic link and the second driving the backup or secondary
fiber optic link.
If a backup fiber optic link mode of operation is not
implemented, BCKPLNK (pin 40) is connected to VCC.
Backup Link Mode is enabled in the primary ML6652 by
connecting a 10kΩ resister in series with an LED from
BCKPLNK (pin 40) with the LED cathode to ground.
Configuring the two ML6652 media converters simply
requires BCKPLNK (pin 40) of the primary device to be
connected to TPOUTOFF# of the secondary device.
A second configuration is suggested to avoid confusion;
that is Pin 40 (BCKPLINK) of the primary ML6652 is
connected to both pin 13 (TPOUTOFF#) and 14
(FOOUTOFF#) of the secondary ML6652, disabling both
copper and fiber outputs. A third configuration, if Pin 24
(PWRDWN#) of the secondary ML6652 is not being used
to control power usage by the system (for example in a
stand alone configuration without system microprocessor
control) Pin 40 (BCKPLINK) of the primary ML6652 can be
connected to Pin 24 (PWRDWN#) of the secondary
ML6652, powering down the secondary ML6652 to save
power.
The primary link is not functioning if a Far End Fault (FEF)
signal is received on the fiber optic differential input pair
FOINP and FOINN as defined in clause 24 of IEEE Std.
802.3-1998, or when the fiber optic signal does not meet
the 100Mbps signal detection constraints.
When Backup Link Mode is enabled, the input and output
signal dependencies are related as shown in Table 8.
Final Datasheet
DS6652-F-02
ML6652