ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 22

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

22
Control Registers
Register 30 Continued
REGISTER 28
15-5
Bit
Bit
CONTROL REGISTERS
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
SINGLESPEED
SEL 10Mbps
LOWITPOUT
SLOWMLT3
FSENSEDIS
Name
SHORTFO
SHORTTP
Name
LONGWL
FEFDSBL
BCKPDIS
Reserved
PECLQU
Reserved
PECLTP
RSTSCR
SCRON
ADDR 11100 (bin)
Description
Description
Set high (1) reduces rise and fall times of MLT-3 outputs on pins
TPOUTP (1) and TPOUTN(3)
Set high (1) disables 100 Mbps PLL frequency sensing circuits
Set high (1) disables Far-End-Fault pattern generation and detection.
Set high (1) disables Backup Link function and overwrites
BCKPLINK (40) configuration setting.
Setting this bit to 1 enables only a single data rate
Setting bit to 1 and SINGLESPEED <30.9> is 1
enables only 10Mbps data rate
Setting bit to 0 and SINGLESPEED <30.9> enables only 100Mbps data rate
Setting bit to 1 causes the interface at FOINP (pin 33),
FOINN (pin 32), IOUT (pin 21), and IOUT# (pin 22) to be PECL/LVPECL
compatible
Setting bit to 1 assumes optical wavelength to be 1300nm
Setting this bit to 0 assumes optical wavelength to be 850nm when the
quantizer/fiber optic LED driver are used.
If PECLQU <30.7> is set to 1 or SHORTFO <30.5> is set to 1 LONGWL is ignored
Setting bit 1 sets up the signal detection circuit for a
fiber maximum link distance of 300 meters in both 10Mbps and
100Mbps modes when the quantizer/fiber optic LED driver is used.
Setting bit to 0 sets up the signal detection circuit for a maximum
link distance of 2Km, when the quantizer/fiber optic LED driver are used.
If PECLQU <30.7> is set to 1 SHORTFO is ignored
Setting bit to 1 causes TPOUTP (pin 1) and TPOUTN (pin 3)
output current to be reduced to 25% of the standard twisted pair
output current. The output remains 100BASE-TX, 10BASE-T, or FLP Bursts.
If PECLTP <30.3> is set to 1, LOWITPOUT is ignored
Setting bit to 1 causes the interface at TPINP (pin 10), TPINN
(pin 11), TPOUTP (pin 1), and TPOUTN (pin 3) to be PECL or
PECL compatible
Setting bit to 1 sets up the twisted pair interface receiver
circuit for a maximum link distance of 10 meters, bypassing the
Unshielded Twisted Pair (UTP-5) equalizer. Setting bit to 0 maintains
the equalizer in the signal path.
If PECLTP <30.3> is set to 1, SHORTTP is ignored
Setting bit to 1 enables scrambler/descrambler function.
Setting bit to 0 disables both functions
Setting bit to 1 forces the scrambler register state to 00000000011 (binary) R/W
Setting bit to 0 releases logic in the scrambler block
January 2004
1C (hex) All bits are Read Write
Final Datasheet
DS6652-F-02
R/W
R/W
ML6652
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PECLQU
PECLQU
PECLTP
PECLTP
PECLTP
SPEED
SPEED
(pin 27)
(pin 27)
PECLTP
Default
Default
Set by
Set by
Set by
Set by
Set by
Set by
Set by
Set by
(pin 7)
(pin 8)
(pin 8)
(pin 8)
(pin 7)
(pin 7)
(pin 7)
Set by
0
0
0
0
0
0
0
0