ml6652 Sirenza Microdevices, ml6652 Datasheet - Page 21

• Manufacturer Part Number: ml6652
• Description: 10/100mbps Ethernet Fiber And Copper Media Converter With Auto-negotiation
• Manufacturer: Sirenza Microdevices

21
Control Registers
Register 31 ADDR 11111 (bin) 1F (hex) All bits are R/W All bits default to 0
Register 30 ADDR 11110 (bin) 1E (hex) All bits are R/W
7-4
3-0
15
14
13
12
11
10
Bit
Bit
15
14
13
12
11
10
CONTROL REGISTERS
TRANSPARENT#
ADVERTHD#
ADVERTFD#
Power Down
FOOUTOFF
LPBKTOFO
TPOUTOFF
LPBKTOTP
Name
Name
PLLLPBK#
Reserved
Reserved
DSBLAN
RESET
LIW
Setting bit to 1 powers down all circuits and resets all
control logic. Register bits are not reset (except the management interface)
and new configuration data is not loaded
Setting bit to 1 turns off the output stage of the Fiber Optic
driver leaving the output pins in a high impedance state.
Setting bit to 1 creates the exact same results as a 0 input on FOUTOFF#
Setting bit to 1 turns off the output stage of the twisted pair
line driver leaving the output pins in a high impedance state. Setting bit
to 1 creates exact same result as 0 input on TPOUTOFF#
Setting bit to 1 directs TPINP (pin 10) and TPINN (pin 11)
to loop back to TPOUTP (pin 1) and TPOUTN (pin 3). Including
the PLL in the 100Mbps signal path is controlled by <31.10>,
PLLLPBK#
Setting bit to 1 directs FOINP (pin 33) and FOINN (pin 32)
to loop back to IOUT (pin 21) and IOUT# (pin 22). Including the
PLL in the 100Mbps signal path is controlled by <31.10> PLLLPBK#.
Setting bit to 1 removes the clock/data recovery PLL from
the signal path during 100Mbps loop back modes
Description
Setting bit to 1 AND TRANSPARENT# <30.11> set to 1
causes Half Duplex capability to be advertised in FLP bursts
Setting bit to 0 AND TRANSPARENT# <30.11> set to 1
causes Half Duplex capability to not be advertised in FLP bursts
Setting TRANSPARENT# <30.11> to 0 causes ADVERTHD#
to be ignored
Setting bit to 1 disables detection of FLNP and FLP bursts
Setting this bit to 1 causes all configuration pins to be read
and all register bits to be initialized 3 to 8µs after the bit is
returned to a 0. The bit is self clearing
Setting this bit to 1 enables the Link Integrity Warning function
Setting bit to 1 enables NON-TRANSPARENT Mode of operation
Setting bit to 0 enables TRANSPARENT Mode of operation
Setting bit to 0 and TRANSPARENT# <30.11> set to 1
causes Full Duplex capability to be advertised in FLP bursts
Setting bits to 1 and TRANSPARENT# <30.11> set to 0
causes Full Duplex capability to not be advertised in FLP bursts
Setting TRANSPARENT# <30.11> to 0 causes ADVERFTD#
to be ignored
Description
January 2004
Final Datasheet
DS6652-F-02
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ML6652
AD4LIW
DUPLEX
DUPLEX
(pin 27)
(pin 25)
(pin 25)
Default
SPEED
(pin 4)
Default
Set by
Set by
Set by
Set by
0
0
0
0
0
0
0
0