hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 25

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

CK / CK
ADDRESS
COMMAND
Rev. 0.2 / Oct. 2005
2.4 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row address A0
through A15 is used to determine which row to activate in the selected bank. The Bank Activate command
must be applied before any Read or Write operation can be executed. Immediately after the bank active
command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W
command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay when the R/W command is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are sup-
ported. Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-
tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (t
commands is t
: “H” or “L”
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
Row Addr.
T0
Bank A
Activate
Bank A
RAS - RAS delay time (
RRD
tRCD =1
Internal RAS-CAS delay (>=
.
Col. Addr.
T1
Post CAS
Bank A
Bank A
Read
CAS-CAS delay time (
additive latency delay (
Bank Active
>= t
RRD
Row Addr.
T2
Activate
Bank B
Bank B
)
t
(>= t
RCDmin
t
RAS
CCD
)
AL
)
)
)
Col. Addr.
T3
Post CAS
Bank B
Bank B
Read
Read Begins
RC
RAS Cycle time (
). The minimum time interval between Bank Activate
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Precharge
Tn
Bank A
Bank A
>= t
Addr.
RC
)
Bank Precharge time (
Tn+1
1HY5PS12421(L)M
HY5PS12821(L)M
Precharge
Tn+2
Bank B
Bank B
>= t
Addr.
RP
)
Row Addr.
Tn+3
Activate
Bank A
Bank A
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