hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 42

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
Burst Write followed by Precharge
Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge
Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion
of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay.
Example 1: Burst Write followed by Precharge: WL = (RL-1) =3
Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4
CK/CK
CMD
DQS/DQS
DQs
CK/CK
CMD
DQS/DQS
DQs
Posted CAS
Posted CAS
WRITE A
WRITE A
T0
T0
T1
T1
NOP
NOP
WL = 3
WL = 4
T2
T2
NOP
NOP
T3
DIN A
T3
NOP
NOP
0
DIN A
1
T4
T4
DIN A
DIN A
NOP
NOP
2
0
DIN A
DIN A
3
1
T5
T5
DIN A
NOP
NOP
Completion of the Burst Write
2
DIN A
3
Completion of the Burst Write
> =
T6
T6
NOP
NOP
WR
1HY5PS12421(L)M
HY5PS12821(L)M
> = t
T7
T7
NOP
NOP
WR
Precharge A
Precharge A
T 8
T 9
42