hy5ps1g821m Hynix Semiconductor, hy5ps1g821m Datasheet - Page 37

• Manufacturer Part Number: hy5ps1g821m
• Description: 1gb Ddr2 Sdram
• Manufacturer: Hynix Semiconductor

Rev. 0.2 / Oct. 2005
2.5.5 Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent
with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and
though used in a uni-directional manner, is internally loaded identically to data bits to insure matched sys-
tem timing. DM of x4 and x16 bit organization is not used during read cycles. However DM of x8 bit organi-
zation can be used as RDQS during read cycles by EMRS(1) settng.
Data Mask Timing
Data Mask Function, WL=3, AL=0, BL = 4 shown
Case 1 : min t
CK
CK
COMMAND
DQS/DQS
DQ
DM
Case 2 : max t
DQS/DQS
DQ
DM
DQS/
DQS
DQ
DM
DQSS
DQSS
Write
t
DS
t
DH
t
DQSS
t
DQSS
t
DS
t
DH
1HY5PS12421(L)M
t
HY5PS12821(L)M
WR
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