hd66789 Renesas Electronics Corporation., hd66789 Datasheet - Page 42

• Manufacturer Part Number: hd66789
• Description: 528-channel, One-chip Driver For Amorphous Tft Panels With 262,144-color Display Ram, Power Supply Circuit, And Gate Circuit
• Manufacturer: Renesas Electronics Corporation.

HD66789
DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in
synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. Frame
frequency can be adjusted in combination with the adjustment of 1H period (RTN 3-0). When changing the
number of drive raster-rows, adjust the frame frequency too. For details, see “Frame Frequency
Adjustment Function”. When the RGB interface is selected, this function is not available.
DIV Bits and Division Ratio
DIV1
0
0
1
1
fosc = R-C oscillation frequency
Formula for the frame frequency
Frame frequency
fosc: R-C oscillation frequency
Line: number of drive raster-rows (NL bit)
Division ratio: DIV bit
Clock cycles per raster-row: RTN bit
FP : the number of raster-rows in the front porch
BP : the number of raster-rows in the back porch
EQ1-0: Equalizing period is prolonged as the number of clocks specified with EQ1-0 bits. The
equalization signal is output only with the alternating current.
EQ Bits
EQ1
0
0
1
1
SDT1-0: Determine the amount of delay for the source output from the falling edge of the gate output.
Rev.0.12, May 09 2003, page 42 of 156
DIV0
0
1
0
1
EQ0
0
1
0
1
Division Ratio
1
2
4
8
Internal Operation
(synchronized with the internal operating clock)
Not equalized
1 clock
2 clocks
3 clocks
=
Clock cycles per raster-row u division ratio u (Line + BP + FP)
Internal Operating Clock Frequency
fosc / 1
fosc / 2
fosc / 4
fosc / 8
Equalizing period
fosc
RGB I/F Operation
(synchronized with DOTCLK )
Not equalized
8 clocks
16 clocks
24 clocks
Preliminary
[Hz]