pallv16v8 Lattice Semiconductor Corp., pallv16v8 Datasheet - Page 19

• Manufacturer Part Number: pallv16v8
• Description: Low Voltage, Zero Power 20-pin Ee Cmos Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

POWER-UP RESET
The PALLV16V8 has been designed with the capability to reset during system power-up. Following
power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the
logic polarity. This feature provides extra flexibility to the designer and is especially valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
t
t
t
PR
S
WL
The V
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Symbol
CC
Registered
Power
Clock
rise must be monotonic.
Output
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
PALLV16V8-10 and PALLV16V8Z-20 Families
2.7 V
Parameter Descriptions
Figure 3. Power-Up Reset Waveform
t
PR
t
WL
t
S
See Switching Characteristics
Min
Max
1000
17713D-16
CC
V
CC
can rise
Unit
ns
19