pallv16v8 Lattice Semiconductor Corp., pallv16v8 Datasheet - Page 3

• Manufacturer Part Number: pallv16v8
• Description: Low Voltage, Zero Power 20-pin Ee Cmos Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

The user is given two design options with the PALLV16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer
will supply device codes for the standard PAL device architectures to be used with the PALLV16V8.
The programmer will program the PALLV16V8 in the corresponding architecture. This allows the
user to use existing standard PAL device JEDEC files without making any changes to them.
Alternatively, the device can be programmed as a PALLV16V8. Here the user must use the
PALLV16V8 device code. This option allows full utilization of the macrocell.
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial output,
combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is
enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a
product term or always enabled. In the dedicated input configuration, it is always disabled. With
the exception of MC
from an adjacent I/O. MC
The macrocell configurations are controlled by the configuration control word. It contains 2 global
bits (SG0 and SG1) and 16 local bits (SL0
whether registers will be allowed. SG1 determines whether the PALLV16V8 will emulate a PAL16R8
family. Within each macrocell, SL0
macrocell, and SL1
The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There
are four multiplexers: a product term input, an enable select, an output select, and a feedback
select multiplexer. SG1 and SL0
*In macrocells MC 0 and MC 7
1 1
0 X
1 0
x
0
sets the output as either active low or active high for the individual macrocell.
and MC
,
SG1 is replaced by SG0 on the feedback multiplexer.
0
derives its input from pin 11 (OE) and MC
7
PALLV16V8-10 and PALLV16V8Z-20 Families
, a macrocell configured as a dedicated input derives the input signal
SG1
x
are the control signals for all four multiplexers. In MC
SL1
x
, in conjunction with SG1, selects the configuration of the
Figure 1. PALLV16V8 Macrocell
X
SL0
0
X
through SL0
CLK
D
7
and SL1
Q
Q
V
CC
OE
0
*SG1
through SL1
7
0 X
1 1
0 X
1 0
1 1
1 1
1 0
0 0
0 1
1 0
from pin 1 (CLK).
SL0 X
7
). SG0 determines
Macrocell
Adjacent
To
0
Adjacent
and MC
From
Pin
17713D-004
I/O
X
7
3
,