pallv16v8 Lattice Semiconductor Corp., pallv16v8 Datasheet - Page 7

• Manufacturer Part Number: pallv16v8
• Description: Low Voltage, Zero Power 20-pin Ee Cmos Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor Corp.

Benefits of Lower Operating Voltage
The PALLV16V8 has an operating voltage range of 3.0V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications. The PALLV16V8 inputs accept up to 5.5 V, so they are safe for mixed voltage design.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise
generation and provides a less hostile environment for board design. A lower operating voltage
also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALLV16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of
the logic.
Register Preload
The register on the PALLV16V8 can be preloaded from the output pins to facilitate functional testing
of complex state machine designs. This feature allows direct loading of arbitrary states, making it
unnecessary to cycle through long test vector sequences to reach a desired state. In addition,
transitions from illegal states can be verified by loading illegal states and observing proper
recovery.
The preload function is not disabled by the security bit. This allows functional testing after the
security bit is programmed.
Security Bit
A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. However, programming and
verification are also defeated by the security bit. The bit can only be erased in conjunction with
the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALLV16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.
Programming and Erasing
The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset
a previously configured device back to its unprogrammed state. Erasure is automatically performed
by the programming hardware. No special erase operation is required.
PALLV16V8-10 and PALLV16V8Z-20 Families
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