mx25l12845e Macronix International Co., mx25l12845e Datasheet - Page 17

• Manufacturer Part Number: mx25l12845e
• Description: Mx25l12845e High Performance Serial Flash Specification Preliminary
• Manufacturer: Macronix International Co.

Note 1: see the Table 2 "Protected Area Size" in page 11.
P/N: PM1428
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (see Figure 15).
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area(as defined in Table 2) of the device to against the program/erase instruction without hardware protection mode
being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruc-
tion to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruc-
tion can be executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP# is
enable. While QE is "1", it performs Quad I/O mode and WP# is disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0". SRWD bit is operat-
ed together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The hardware protection
mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write
Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP3,
BP2, BP1, BP0) are read only.
Status Register
SRWD (status
register write
register write
Non-volatile
1=status
protect)
disable
bit7
bit
0=not Quad
Non-volatile
1= Quad
Enable)
Enable
Enable
(Quad
bit6
QE
bit
Non-volatile
protected
(level of
(note 1)
block)
BP3
bit5
bit
Non-volatile
protected
(level of
(note 1)
block)
BP2
bit4
bit
17
Non-volatile
protected
(level of
(note 1)
block)
BP1
bit3
bit
Non-volatile
protected
MX25L12845E
(level of
(note 1)
block)
BP0
bit2
bit
(write enable
0=not write
volatile bit
1=write
enable
enable
latch)
WEL
bit1
REV. 0.06, MAR. 05, 2009
0=not in write
progress bit)
volatile bit
operation
operation
(write in
1=write
WIP
bit0