mx25l3255d Macronix International Co., mx25l3255d Datasheet - Page 19

• Manufacturer Part Number: mx25l3255d
• Description: Security Serial Flash
• Manufacturer: Macronix International Co.

MX25L3255D
(7) Chip Unprotect (UNLOCK)
The UNLOCK instruction is for disabling the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing UNLOCK instruction.
The sequence of issuing UNLOCK instruction is: CS# goes low → send UNLOCK (F3h) instruction → CS# goes
high. (see Figure 14)
The CS# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
(8) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out. (see Figure 15)
(9) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code->
3-byte address on SI→ 1-dummy byte (default) address on SI→data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out. (see Figure 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(10) 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address inter-
leave on SIO1 & SIO0→ 4-bit dummy cycle on SIO1 & SIO0→data out interleave on SIO1 & SIO0→ to end 2READ
operation can use CS# to high at any time during data out (see Figure 18 for 2 x I/O Read Mode Timing Waveform).
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1431
REV. 0.03, MAR. 13, 2009
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