m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 189

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

PULSE OUTPUT PORT MODE
9.2 Block description of pulse output port 0
Fig. 9.2.3 Structures of three-phase output data registers 0, 1 (pulse output port 0)
9-8
9.2.2 Three-phase output data registers 0, 1
Figure 9.2.3 shows the structures of three-phase output data registers 0, 1 (pulse output port 0).
Three-phase output data register 1 (Address A9
Note: Invalid in pulse mode 1.
Three-phase output data register 0 (Address A8
Note: Invalid in pulse mode 0.
7, 6
Bit
Bit
0
1
2
3
4
5
0
1
2
3
4
5
6
7
RTP0
RTP0
RTP0
RTP0
RTP1
(Valid in pulse mode 1.) (Note)
RTP1
(Valid in pulse mode 1.) (Note)
Pulse output trigger select bits
Pulse width modulation enable
bit 0
Pulse width modulation enable
bit 1
Pulse width modulation enable
bit 2
Pulse output polarity select bit
RTP1
(Valid in pulse mode 0) (Note)
RTP1
(Valid in pulse mode 0) (Note)
RTP1
RTP1
0
1
2
3
0
1
0
1
2
3
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
pulse output data bit
Bit name
Bit name
7905 Group User’s Manual Rev.1.0
b7 b6
0 0 : Underflow of timer A0
0 1 : Falling edge of input signal to pin RTP
1 0 : Rising edge of input signal to pin RTP
1 1 : Both falling and rising edges of input signal to
0 : “L” level output
1 : “H” level output
0 : No pulse width modulation by timer A2
1 : Pulse width modulation by timer A2
0 : No pulse width modulation by timer A4
1 : Pulse width modulation by timer A4
0 : Positive
1 : Negative
0 : “L” level output
1 : “H” level output
0 : No pulse width modulation by timer A1
1 : Pulse width modulation by timer A1
pin RTP
16
16
)
)
TRG0
Function
Function
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
TRG0
TRG0
At reset
At reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW