m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 29

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
Fig. 2.1.4 Setting examples of direct page area
2-6
2.1.8 Direct page register 0 to 3 (DPR0 to DPR3)
Each of direct page registers 0 to 3 (hereafter called the “DPRi”) is a 16-bit register. The contents of this
register specify the direct page area in bank 0
addressing modes use DPRi.
The contents of the DPRi indicate the base address (the lowest address) of the direct page area. The direct
page area is specified in the space above this address.
After reset, whether to use DPR0 only or DPR0 to DPR3 can be selected by the direct page register switch
bit. (See Figure 2.1.5). This selection specifies the direct page area. Table 2.1.1 lists the selection of the
direct page register. Figure 2.1.4 shows setting examples of the direct page area.
At reset, DPR0 = “0000
Addressing modes using direct page register
• Direct
• Direct indexed X
• Direct indexed Y
• Direct indirect
• Direct indexed X indirect
• Direct indirect indexed Y
• Direct indirect long
• Direct indirect long indexed Y
• Direct bit relative
Refer to “7900 Series Software Manual” for addressing modes and instructions.
Note: When the low-order 8 bits of DPRi = “00,” the number of cycles required for address generation becomes 1 cycle smaller.
Bank 0
Bank 1
Direct page register switch bit = 0
The direct page area is specified in space across banks 0
and
10000
FFFF
16
16
1
16
0
when
16
16
16
DPR0 is “FF01
16
1000F
123
222
FF10
,” and each of DPR1 to DPR3 becomes undefined.
0
FF
16
16
16
16
16
” or more.
16
16
When DPR0 = 0000
When DPR0 = 0123
When DPR0 = FF10
7905 Group User’s Manual Rev.1.0
16
16
16
16
or in the space across banks 0
16
Bank 0
Bank 1
Table 2.1.1 Selection of direct page register
Usable DPRi
Direct page area
Direct page register switch bit = 1
The direct page area is specified in the space across banks 0
and
10000
FFFF
16
16
1
16
0
when
16
16
16
DPRi is “FFC1
1000F
0
3F
40
7F
800
83F
FFD0
Direct page register switch bit
16
16
16
16
16
16
16
” or more.
256 bytes
16
16
DPR0
16
0
When DPR0 = 0000
When DPR1 = 0040
When DPR3 = FFD0
When DPR2 = 0800
and 1
16
. The following
DPR0 to DPR3
64 bytes at
each DPRi
1
16
16
16
16
16