act7006 Aeroflex Circuit Technology, act7006 Datasheet
act7006
Available stocks
Related parts for act7006
act7006 Summary of contents
Page 1
... Internal hybrid logic removes all critical timing imposed on a typical subsystem, thereby simplifying the implementation of this interface. BUS "0" DUAL TX/RX BUS "1" echnology eroflex Circuit T ACT7005/7006 General Description 1553 PROTOCOL ACT7005 / ACT7006 Block Diagram – Data Bus Modules For The Future © SCD7005 REV B 8/2/01 CIRCUIT TECHNOLOGY www.aeroflex.com INTERRUPTS/ CONTROL SIGNALS µP S INTERFACE U ...
Page 2
... Aeroflex Circuit Technology 2 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 ...
Page 3
... Total supply current transmitting at 1MHz into a 35Ω load at Point A in Figure Note: 1/ Decreases linearly to applicable "standyby" values at zero duty cycle. 2/ Represents one channel only. Table 2 – Analog Transceiver Power Supply Characteristics Aeroflex Circuit Technology ) +125°C Symbol I CC ...
Page 4
... Output Offset at point A in Figure 4, 2.5µs after mid-bit crossing of parity bit of last word of a 660µs message Rise and Fall times (10% to 90% of p-p output) Table 4 – Analog Transceiver Electrical Characteristics (Transmitter Section) Aeroflex Circuit Technology Point A Point C Point A Point C (Over Full Temperature Range) Symbol 140Ω ...
Page 5
... A. VDD = 4.5V and IOH = 3mA B. VDD = 5.5V and IOL = 3mA 4. VDD = 5.5V A. Clock Input = 6MHz (45-55% Duty Cycle / TTL Levels), All remaining inputs = VDD, All Outputs = Open Circuit B. During a 32 word FIFO to RAM or RAM to FIFO block Table 5 – Logic Electrical Characteristics Aeroflex Circuit Technology Min Typ 4.5 5.0 2.4 Input I -450 ...
Page 6
... ACT7005/7006 TX DATA CH A/B GND TX DATA CH A/B Figure 2 – Transformer Configuration Aeroflex Circuit Technology } Taps at N1:N3 For CT Stub Coupling (See Table) (N1 : N2) (See Table) TURNS RATIO N1:N2 N1:N3 Technitrol Part # 6 0.75Z O For Direct Coupling 0.75Z O ACT7005/7006 1:2.5 1:1.79 T-1553-45 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 ...
Page 7
... R3 0.75Z R4 0.75Z O TRANSFORMER-COUPLED RT CONFIGURATION (LONG-STUB) Zo, 2% TRANSCEIVER A TRANSCEIVER B Figure 3 – Typical Interface Connections Aeroflex Circuit Technology +5V + D15 DATA D14 2 43 GND D13 D12 3 40 DATA D11 D10 DATA D8 2 ...
Page 8
... Series incorporates a single +5VDC only transceiver. The protocol section internally interfaces to the transceivers. Control of the transceivers is provided Aeroflex Circuit Technology by the protocol section. This is determined by which bus the command word was received on in the remote terminal mode the bus controller mode, which bus was selected for transmission by the state of a bit in the operation register ...
Page 9
... While in this mode, the upper byte (8 bits) of the operation register controls Bus Control functionality. This includes TEST/NORMAL operation Aeroflex Circuit Technology commands, BUS selection and RETRY initialization of a faulty transaction. A typical Bus Control transaction would operate as ...
Page 10
... Select and Auto Retry), and contains information for reading or writing data to the Internal RAM. (See note below.) This register also provides Aeroflex Circuit Technology software control of the DBCACC, SERVREQ, and SSERR bits of the status word. Following power-up master reset, bit 7 of this register will be set high. ...
Page 11
... The word count and subaddress lines for the current command are valid when INCMD goes low. The subsystem must then determine whether or not Aeroflex Circuit Technology the word count or subaddress considered illegal by the RT. If either of them is considered illegal, the subsystem must produce a negative-going pulse called MEREQ ...
Page 12
... Last Command or Transmit Status immediately following the fault. It will also prevent resetting the TF and SSF Bits in the Status Word. Any other valid commands will cause those BIT Word Bits and the Status Word Bits to be reset. Aeroflex Circuit Technology 12 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 ...
Page 13
... OUTPUT FIFO buffer command. The BUFF EF flag will go high when the first word is loaded into the OUTPUT FIFO buffer. The word may be read at that time. Please see Figure 6. MODERESET Indicates reception of a valid RESET mode command. Table 6 – Discrete Interrupts Summary Aeroflex Circuit Technology 13 SCD7005 REV B 8/2/01 Plainview NY (516) 694-6700 ...
Page 14
... Between 1 and 32 data words must be loaded in the input FIFO buffer when using an EXECUTE command with this bit set. 2. SET LOW: OUTPUT OPERATION EXECUTE operation will transfer a complete block of data (32 words) to the output FIFO buffer from the specified subaddress of internal RAM. Aeroflex Circuit Technology SUBADDRESS BIT SA0 (LSB) SAl SA2 ...
Page 15
... Dynamic Bus Control Accept/Auto-Retry Bus Bit. Auto-Retry Other Bus Table 7 – Operational Register (continued) Aeroflex Circuit Technology RT MODE: A LOW in this bit will cause the service request bit in the status word to be set. BC MODE: This is the LSB of the Auto-Retry options. See table on this page, Bit 14 A LOW in this bit will cause a Subsystem Error Bit in the status word to be set ...
Page 16
... This signal executes the desired Bus Controller Function or test of the protocol section determined by the Operation Register. Table 8 – Non-Register Operational Commands Aeroflex Circuit Technology 1. I/O BIT HIGH Data currently in INPUT FIFO BUFFER is loaded into the INTERNAL RAM block specified by the T/R BIT and SUBADDRESS FIELD of the OPERATION REGISTER ...
Page 17
... Read Status Word #2/RMD Reg. Low Byte Write Command Word #1 Reg. High Byte Write Command Word #1 Reg. Low Byte Write Command Word #2/AMD Reg. High Byte Write Command Word #2/AMD Reg. Low Byte Trigger Transaction Table 9 – 8-Bit Mode I/O Operations Aeroflex Circuit Technology AD3 x x ...
Page 18
... Read SYNC Data Register Write Vector Word Register BC MODE ONLY Read Status Word #1 Register Read Status Word #2/RMD Register Write Command Word #1 Register Write Command Word #2/AMD Register Trigger Transaction Table 10 – 16-Bit Mode I/O Operations Aeroflex Circuit Technology AD3 AD2 ...
Page 19
... Table 11 – Pin Number Description Aeroflex Circuit Technology Signal Description Digital Supply Voltage Digital Supply Voltage Digital Grounds N/C - ACT7005, SERR on ACT7006 - Subsystem Error. When low sets the SSF Bit in the RT’s return status word. Digital Grounds Transceiver A +5VDC Supply Voltage Digital Ground A Analog Ground A ...
Page 20
... DBCREQ DONE Table 11 – Pin Number Description (continued) Aeroflex Circuit Technology Signal Description 6 MHz Master Clock. DATA CHANNEL A. (BUS 0). This is the combined signals, RX Data In and TX Data Out, that connect to the IN phase primary terminal of the Bus Transformer. DATA CHANNEL A. (BUS 0) This is the combined signals RX Data In and TX Data Out, that connect to the OUT of phase primary terminal of the Bus Transformer ...
Page 21
... RTAD2 19 RTAD3 18 RTAD4 Table 11 – Pin Number Description (continued) Aeroflex Circuit Technology Signal Description Enable. When held low, enables Bit Decode, Next Status, and Status Update program lines. Good Block (RT) / VALID TRANSFER (BC) VALID Transmit (RT) / INVALID TRANSFER (BC) Loop Test Fail. This line goes low if any error in the terminals own transmitted waveform is detected or if any parity error in the hardwired RT address is detected ...
Page 22
... WT 6 INCMD Table 11 – Pin Number Description (continued) Aeroflex Circuit Technology Signal Description Remote Terminal Address Error. This line goes low if an error is detected in the RT address parity of the selected receiver. Any receiver detecting an error in the RT address will turn itself off. Subaddress. These five lines are a label for the data being transferred ...
Page 23
... DH WPW t = 10nsec for 50nsec < Read pulse time t RPW or RD may go low or return high first. 4. Refer to “Discrete Interrupt” text for further information. Table 12 – AC Electrical Characteristics Aeroflex Circuit Technology Min 140 100 = +5.0V ± 10 the time when both DS and WT are simultaneously low ...
Page 24
... I/O Write Timing DS WT AD0 - AD3 DB0 - DBF I/O Read Timing DS RD AD0 - AD3 DB0 - DBF Output Interrupts GOOD BLOCK SYNC W/DATA SYNC NO DATA VALID TRANS Figure 4 – Subsystem Interface Timing Aeroflex Circuit Technology t WPW RPW IPW 24 t REC t AH ...
Page 25
... RD READ STROBE Must GO LOW together with DS to perform a READ OPERATION. NOTE: WT STROBE MUST BE HIGH. INTERRUPTS Refer to DISCRETE INTERRUPT TABLE. Table 13 – Subsystems Interface Signals Aeroflex Circuit Technology 8 BIT MODE DB0/DB8 = LSB DB7/DB15 = MSB DB4 TO DB12 DB5 TO DB13 DB6 TO DB14 DB7 TO DB15 ...
Page 26
... LOAD FIFO WITH DATA EXECUTE OPERATION DONE INTERRUPT ? YES DONE Figure 5 – Flowchart # 1 – Load Data into Transmit RAM Aeroflex Circuit Technology SET: SUBADDRESS BITS @ ADDRESS = 0 T/R BIT = 1 I/O BIT = 1 RESET INPUT FIFO @ ADDRESS = B LOAD INPUT FIFO @ ADDRESS = E (MAX = 32 WORDS) WRITE AN ARBITRARY WORD ...
Page 27
... NO INTERRUPT ? YES READ OUTPUT FIFO DONE Figure 6 – Flowchart # 2 - Unload Data from Receive RAM Aeroflex Circuit Technology SET: SUBADDRESS BITS @ ADDRESS = 0 T/R BIT = 0 (16 BIT MODE) I/O BIT = 0 RESET OUTPUT FIFO @ ADDRESS = D WRITE AN ARBITRARY WORD TO ADDRESS = 8 *FIFO CAN BE READ OUT BEFORE THE DONE INTERRUPT. FIFO READ CAN COMMENCE AS SOON AS THE BUFF EF SIGNAL GOES HIGH ...
Page 28
... NEXT STATUS 27 STATUS UPDATE 28 MODE 16/8 29 TEST1 30 TEST2 Table 14 – ACT7005 / 7006 DIP Package Pinouts Aeroflex Circuit Technology Pin Function # 31 RESET [MASTER] 32 RTADER 33 LTFAIL 34 N/C - ACT7005 / SERR - ACT7006 35 VECTOR 36 SYNCND 37 SYNCWD (A) [TX/RX / LOGIC N/C 40 DATA OUTPUT GND A 42 DATA ANALOG GND A ...
Page 29
... Model Number ACT7005 ACT7006 Lead 1 & ESD Designator .090 .135 Pin 3 Pin 1 Pin 2 1.300 1.100 Pin 89 Pin 90 Pin 88 .135 Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com Aeroflex Circuit Technology ...