act7006 Aeroflex Circuit Technology, act7006 Datasheet - Page 14

• Manufacturer Part Number: act7006
• Description: Act7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem
• Manufacturer: Aeroflex Circuit Technology

Name
VECTOR
DBCREQ
RETRY
SELF TEST
PASS
Bit
0-4
Aeroflex Circuit Technology
5
6
Name
SA BITS
T/R BIT
I/O
Table 6 – Discrete Interrupts Summary (continued)
Function
SUBADDRESS BITS
Define SUBADDRESS MESSAGE BLOCK in INTERNAL RAM.
BIT
These bits correspond directly to 1553B definition in the command word.
Although SUBADDRESSES 00000
blocks specified by them are both READABLE and WRITABLE by the
SUBSYSTEM. They are not accessible from the 1553B BUS.
TRANSMIT/RECEIVE BIT points INPUT/OUTPUT OPERATIONS to either the
TRANSMIT SECTION or RECEIVE SECTION of the INTERNAL RAM.
INPUT/OUTPUT BIT DEFINES DIRECTION OF DATA TRANSFER
0
1
2
3
4
1. SET HIGH: INPUT OPERATION
2. SET LOW: OUTPUT OPERATION
An EXECUTE operation will transfer the Data currently loaded in the input
FIFO buffer to the specified message block (SUBADDRESS) in the internal
RAM.
Between 1 and 32 data words must be loaded in the input FIFO buffer when
using an EXECUTE command with this bit set.
EXECUTE operation will transfer a complete block of data (32 words) to the
output FIFO buffer from the specified subaddress of internal RAM.
Use
Indicates that a transmit VECTOR mode command has been received.
VECTOR DATA is transmitted from VW/CMD WD #2/AMD Register.
Indicates acceptance of DYNAMIC BUS CONTROL COMMAND REQUEST
Note: RTU will not accept valid DBC mode command unless DBCACC bit
is set low in the OPERATION Register.
Indicates that an error has occurred in the data transfer and that a retry will be
performed if the retry option is selected. If all retries that were selected fail,
INVALID TRANSFER INTERRUPT would be asserted on the final failure.
Indicates that the INITIATE SELF TEST mode command is being serviced.
Active low pulse output signal which indicates that a sub-system initiated
self-test (on-or off-line) operation has been sucessfully completed. This
interrupt will be issued approximately 90µs after the self-test operation has
been triggered.
Table 7 – Operational Register
SUBADDRESS BIT
SA0 (LSB)
SAl
SA2
SA3
SA4 (MSB)
14
B
and 11111
SCD7005 REV B 8/2/01
B
are illegal in 1553B, message
Plainview NY [phone]