HEF4011BT,653 NXP Semiconductors, HEF4011BT,653 Datasheet
HEF4011BT,653
Specifications of HEF4011BT,653
HEF4011BTD-T
HEF4011BTD-T
Related parts for HEF4011BT,653
HEF4011BT,653 Summary of contents
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HEF4011B Quad 2-input NAND gate Rev. 4 — 30 March 2011 1. General description The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates ...
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... NXP Semiconductors 5. Functional diagram 001aan874 Fig 1. Functional diagram 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 10 HEF4011B Product data sheet Fig HEF4011B 001aan876 Description input input output ground (0 V) supply voltage All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol Parameter V supply voltage DD I input clamping current IK V input voltage ...
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... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter Conditions I < 1 A V HIGH-level IH O input voltage I < 1 A V LOW-level IL O input voltage I < 1 A V HIGH-level OH O output voltage I < 1 A ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics for waveforms see amb Symbol Parameter t propagation delay pd HIGH to LOW output transition time 10 + 1.00 THL LOW to HIGH output transition time 10 + 1.00 TLH [1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and Fig 4. Propagation delay, output transition time Table 9. Measurement points Supply voltage Test data is given in Table Definitions for test circuit: DUT = Device Under Test load capacitance including jig and probe capacitance termination resistance should be equal to the output impedance Z T Fig 5 ...
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... NXP Semiconductors 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Temperature range maximum increased from 85 C to 125 C throughout the data sheet. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: HEF4011B Product data sheet 16 ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline ...